Texas Instruments CC112 Series, User Manual, Page: 19 / 109

CC112X/CC1175
SWRU295C Page 19 of 108
The GPIOs can also be used as inputs by setting
IOCFGx.GPIOx_CFG = HIGHZ (
48). Table 9
shows which signals can be input to the
CC112X.
GPIO Pin Signal Name Signal Description
0 SERIAL_TX Serial data (TX mode) . Used for both synchronous and transparent mode.
Synchronous serial mode: Data is captured on the rising edge of the serial clock
1 - 2 Reserved
3 EXT_32K_CLOCK External 32 kHz clock signal
Table 9: GPIO Input Pin Mapping
3.4.1 MCU Input/Interrupt
There are two main methods that can be used to generate an input/interrupt to the MCU
1. GPIO Signals
2. MARC MCU WAKEUP
3.4.1.1 GPIO Signals
See Table 10 for the different signals that can be output from the
CC112X
. Note that all signals
described as a pulse are two XOSC periods long.
GPIOx_CFG Signal Name Description
0 RXFIFO_THR Associated to the RX FIFO. Asserted when the RX FIFO is filled above
FIFO_CFG.FIFO_THR
. De-asserted when the RX FIFO is drained below
(or is equal) to the same threshold
1 RXFIFO_THR_PKT Associated to the RX FIFO. Asserted when the RX FIFO is filled above
FIFO_CFG.FIFO_THR
or the end of packet is reached. De-asserted
when the RX FIFO is empty
2 TXFIFO_THR Associated to the TX FIFO. Asserted when the TX FIFO is filled above
(or is equal to) (127
− FIFO_CFG.FIFO_THR
). De-asserted when the TX
FIFO is drained below the same threshold
3 TXFIFO_THR_PKT Associated to the TX FIFO. Asserted when the TX FIFO is full. De-
asserted when the TX FIFO is drained below
(127
− FIFO_CFG.FIFO_THR
)
4 RXFIFO_OVERFLOW Asserted when the RX FIFO has overflowed. De-asserted when the RX
FIFO is flushed (see Section 3.2.4)
5 TXFIFO_UNDERFLOW Asserted when the TX FIFO has underflowed. De-asserted when the TX
FIFO is flushed (see Section 3.2.4)
6 PKT_SYNC_RXTX RX: Asserted when sync word has been received and de-asserted at the
end of the packet. Will de-assert when the optional address and/or
length check fails or the RX FIFO overflows/underflows.
TX: Asserted when sync word has been sent, and de-asserted at the end
of the packet. Will de-assert if the TX FIFO underflows/overflows
7 CRC_OK Asserted simultaneously as
PKT_CRC_OK
. De-asserted when the first
byte is read from the RX FIFO
8 SERIAL_CLK Serial clock (RX and TX mode). Synchronous to the data in synchronous
serial mode. Data is set up on the falling edge in RX and is captured on
the rising edge of the serial clock in TX
9 SERIAL_RX Serial data (RX mode). Used for both synchronous and transparent
mode.
Synchronous serial mode: Data is set up on the falling edge.
Transparent mode: No timing recovery (outputs just the hard limited
baseband signal)
10 Reserved (used for test)
11 PQT_REACHED Preamble Quality Reached. Asserted when the quality of the preamble is
above the programmed PQT value (see Section 5.7)
12 PQT_VALID Preamble quality valid. Asserted when the PQT logic has received a
sufficient number of symbols (see Section 5.7)