Texas Instruments CC112 Series, User Manual, Page: 21 / 109

CC112X/CC1175
SWRU295C Page 21 of 108
33 RSSI_STEP_FOUND
Collision indication: RSSI step detected after a sync word is found
(
SYNC_EVENT
asserted). The RSSI step is either 3 or 6 dB (configured
through
AGC_CFG3.RSSI_STEP_THR
)
34 RSSI_STEP_EVENT RSSI step detected (single cycle pulse)
35 Reserved (used for test)
36 ANTENNA_SELECT Antenna diversity control. Can be used to control external antenna
switch. If differential signal is needed, two GPIOs can be used with one
of them having
IOCFGx.GPIOx_INV
set to 1
37 MARC_2PIN_STATUS[1] Partial MARC state status
MARC_2PIN_STATUS[1] MARC_2PIN_STATUS[0] State
0 0 SETTLING
0 1 TX
1 0 IDLE
1 1 RX
38 MARC_2PIN_STATUS[0] See MARC_2PIN_STATUS[1]
39 3 Reserved (used for test)
2 TXFIFO_OVERFLOW Asserted when the TX FIFO has overflowed. De-asserted when the TX
FIFO is flushed (see Section 3.2.4)
1 Reserved (used for test)
0 RXFIFO_UNDERFLOW Asserted when the RX FIFO has underflowed. De-asserted when the RX
FIFO is flushed (see Section 3.2.4)
40 3 MAGN_VALID New CORDIC magnitude sample
2 CHFILT_VALID New channel filter sample
1 RCC_CAL_VALID RCOSC calibration has been performed at least once
0 CHFILT_STARTUP_VALID Channel filter has settled
41 3 COLLISION_FOUND Asserted if a sync word is found during packet reception (i.e. after
PKT_SYNC_RXTX
has been asserted) if
MDMCFG1.COLLISION_DETECT_EN = 1
2 SYNC_EVENT Sync detect (pulse)
1 COLLISION_FOUND Same as 3
0 COLLISION_EVENT Sync found during receive (pulse)
42 PA_RAMP_UP Asserted when ramping is started (for compliance testing)
43 3 CRC_FAILED Packet CRC error
2 LENGTH_FAILED Packet length error
1 ADDR_FAILED Packet address error
0 UART_FRAMING_ERROR Packet UART framing error
44 AGC_STABLE_GAIN AGC has settled to a gain. The AGC gain is reported stable whenever
the current gain setting is equal to the previous gain setting. This
condition is evaluated each time a new internal RSSI estimate is
computed (see Figure 14)
45 AGC_UPDATE A pulse occurring each time the front end gain has been adjusted
(
see Figure 14)
46 ADC data (test purposes only)
3 ADC_CLOCK ADC clock
2 ADC_Q_DATA_SAMPLE ADC sample (Q data)
1 ADC_CLOCK ADC clock
0 ADC_I_DATA_SAMPLE ADC sample (I data)
47 Reserved (used for test)