CC112X/CC1175
SWRU295C
Page 14 of 108
Extended Register Space (0x6F - 0x8C)
Retention
0x6F
IQIE_Q1
No
0x70
IQIE_Q0
No
0x71
RSSI1
No
0x72
RSSI0
No
0x73
MARCSTATE
No
0x74
LQI_VAL
No
0x75
PQT_SYNC_ERR
No
0x76
DEM_STATUS
No
0x77
FREQOFF_EST1
No
0x78
FREQOFF_EST0
No
0x79
AGC_GAIN3
No
0x7A
AGC_GAIN2
No
0x7B
AGC_GAIN1
No
0x7C
AGC_GAIN0
No
0x7D
SOFT_RX_DATA_OUT
No
0x7E
SOFT_TX_DATA_IN
No
0x7F
ASK_SOFT_RX_DATA
No
0x80
RNDGEN
No
0x81
MAGN2
No
0x82
MAGN1
No
0x83
MAGN0
No
0x84
ANG1
No
0x85
ANG0
No
0x86
CHFILT_I2
No
0x87
CHFILT_I1
No
0x88
CHFILT_I0
No
0x89
CHFILT_Q2
No
0x8A
CHFILT_Q1
No
0x8B
CHFILT_Q0
No
0x8C
GPIO_STATUS
No
Extended Register Space (0x8D - 0xD9)
Retention
0x8D
FSCAL_CTRL
No
0x8E
PHASE_ADJUST
No
0x8F
PARTNUMBER
No
0x90
PARTVERSION
No
0x91
SERIAL_STATUS
No
0x92
RX_STATUS
No
0x93
TX_STATUS
No
0x94
MARC_STATUS1
No
0x95
MARC_STATUS0
No
0x96
PA_IFAMP_TEST
No
0x97
FSRF_TEST
No
0x98
PRE_TEST
No
0x99
PRE_OVR
No
0x9A
ADC_TEST
No
0x9B
DVC_TEST
No
0x9C
ATEST
No
0x9D
ATEST_LVDS
No
0x9E
ATEST_MODE
No
0x9F
XOSC_TEST1
No
0xA0
XOSC_TEST0
No
0xA1 - 0xD1
Not Used
0xD2
RXFIRST
No
0xD3
TXFIRST
No
0xD4
RXLAST
No
0xD5
TXLAST
No
0xD6
NUM_TXBYTES
No
0xD7
NUM_RXBYTES
No
0xD8
FIFO_NUM_TXBYTES
No
0xD9
FIFO_NUM_RXBYTES
No
Table 5: Extended Register Space Mapping
3.2.2
Command Strobes
Command Strobes may be viewed as single byte instructions to
CC112X
. By addressing a command
strobe register, internal sequences will be started. These commands are used to enable receive and
transmit mode, enter SLEEP mode, disable the crystal oscillator, etc. The command strobes are listed
in Table 6.The command strobe registers are accessed by transferring a single header byte (no data
is being transferred). That is, only the R/W
¯ bit, the burst access bit (set to 0), and the six address bits
(in the range 0x30 through 0x3D) are written. When sending a strobe, the R/W
¯ bit can be either one
or zero. The status byte is available on the SO pin when a command strobe is being sent.