Texas Instruments CC112 Series, User Manual, Page: 11 / 109

CC112X/CC1175
SWRU295C Page 11 of 108
Access type Command/Address byte Description
Burst Register Access
(extended register space) Command : R/W ¯ 1 1 0 1 1 1 1
Address : A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
(A
7 - 0
: See Table 5)
This access mode starts with a specific command
(0x2F)
The first byte following this command is interpreted as
the extended address
Consecutive bytes are expected after the extended
address byte and the burst access is terminated by
setting CSn high
When the extended address is sent on the SI line, SO
will return all zeros. The chip status byte is returned on
the SO line when the command is transmitted as well as
when data are written to the extended address.
If the internal address counter reaches address 0xFF
(last byte in extended register space) the counter will
wrap around to 0x00
Registers not listed in Table 5 can be part of a burst
access
Command Strobe Access Address : R/W ¯ 0 A
5
A
4
A
3
A
2
A
1
A
0
(0x30 ≤ A
5 - 0
≤ 0x3D)
Accessing one of the command strobe registers triggers
an event determined by the address in A
5 - 0
, e.g.
resetting the device, enabling the crystal oscillator,
entering TX, etc. No data byte is expected.
The chip status byte is returned on the SO line when a
command strobe is sent on the SI line
Direct FIFO Access Command : R/W ¯ B 1 1 1 1 1 0
Address : A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
A
7 - 0
< 0x80: TX FIFO
0x80 ≤ A
7 - 0
≤ 0xFF: RX FIFO
This access mode starts with a specific command
(0x3E) which makes it possible to access the FIFOs
directly through memory operations without affecting the
FIFO pointers.
The first byte following this command is interpreted as
the FIFO address. The next byte is read/written to this
address. If burst is enabled, consecutive bytes will be
read/written by incrementing the address.
1
FIFO pointers are available in extended register space
for debug purposes.
Standard FIFO Access Address : R/W ¯ B 1 1 1 1 1 1 The R/W ¯ bit determines whether the operation is a read
(1) operation from the RX FIFO or a write (0) operation
to the TX FIFO. If the burst bit B is 1, all bytes following
the address byte are treated as data bytes until CSn
goes high. If the burst bit B is 0, the FIFOs are
accessed byte-wise as a normal register.
Table 3: SPI Access Types
1
Note that the first byte received in an empty RX FIFO will not be possible to read using direct FIFO
access. Please see Section 3.2.3 for more details.