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CC112X/CC1175
SWRU295C
Page 20 of 108
13
RSSI_VALID
RSSI calculation is valid
14
RSSI Signals
3
RSSI_UPDATE
A pulse occurring each time the RSSI value is updated (
2
RSSI_UPDATE
A pulse occurring each time the RSSI value is updated (
1
AGC_HOLD
AGC waits for gain settling
(
see Figure 14)
0
AGC_UPDATE
A pulse occurring each time the front end gain has been adjusted
(
15
Clear channel assessment
3
CCA_STATUS
Current CCA status
2
TXONCCA_DONE
A pulse occurring when a decision has been made as to whether the
channel is busy or not. This signal must be used as an interrupt to the
MCU. When this signal is asserted/de-asserted,
can
be checked
1
CCA_STATUS
Current CCA status
0
TXONCCA_FAILED
TX on CCA failed
16
CARRIER_SENSE_VALID
is valid
(
17
CARRIER_SENSE
Carrier sense. High if RSSI level is above threshold (see section 5.8.1)
(
18
DSSS signals for DSSS repeat mode (RX).
MODCFG_DEV_E.MODEM_MODE = 01b
3
DSSS_CLK
DSSS clock (see Section 4.1.6 for more details)
2
DSSS_DATA0
DSSS data0 (see Section 4.1.6 for more details)
1
DSSS_CLK
DSSS clock (see Section 4.1.6 for more details)
0
DSSS_DATA1
DSSS data1 (see Section 4.1.6 for more details)
19
PKT_CRC_OK
PKT_CFG1.CRC_CFG = 01b or 10b
and a good
packet is received. This signal is always on if the radio is in TX or if the
radio is in RX and
PKT_CFG1.CRC_CFG = 00b
. The signal is de-
asserted when RX mode is entered and
PKT_CFG1.CRC_CFG ≠ 00b
20
MARC_MCU_WAKEUP
MCU wake up signal. Read
the cause of the wake up event (see Section 3.4.1.2 for more details)
21
SYNC_LOW0_HIGH1
DualSync Detect. Only valid when
SYNC_CFG0.SYNC_MODE = 111b
.
When
is asserted this bit can be checked to see which
sync word is found
22
Reserved (used for test)
23
LNA_PA_REG_PD
Common regulator control for PA and LNA. Indicates RF operation
24
LNA_PD
Control external LNA
2
25
PA_PD
Control external PA
26
RX0TX1_CFG
Indicates whether RF operation is in RX or TX (this signal is 0 in IDLE
state)
27
Reserved (used for test)
28
IMAGE_FOUND
Image detected by image rejection calibration algorithm
29
CLKEN_SOFT
Data clock for demodulator soft data (see Section 4.1.4 for more details)
30
SOFT_TX_DATA_CLK
Data clock for modulator soft data (see Section 4.1.4 for more details)
31 - 32
Reserved (used for test)
2
This signal is active low. To control an external LNA, PA, or RX/TX switch in applications where the
SLEEP state is used it is therefore recommended to map this signal to GDO3 as this signal will be
hardwired to 1(0) in the SLEEP state.