Quick Start
Figure 18. AutoSync Panel
•
DR
– Disable DCLK Reset – When checked (default) disables the DCLK Reset feature
•
DOC
- Disable Output reference Clocks – When checked (default) disables the AutoSync reference
output clocks. When un-checked a CLK/4 signal is sent on the RCOut1 and RCOut2 outputs.
•
ES
– Enable Slave mode – When checked configures this ADC as an AutoSync slave device.
•
Select Phase
– Selects the Phase of the incoming reference clock used by the AutoSync feature.
•
Reference Clock Delay
– This selects the additional delay added to the input reference clock.
Settings are 0d (0s) to 319d (1000ps). Settings higher than 319d will give 1000ps delay.
Note:
No changes will take effect until the
Write AutoSync Reg
button is clicked.
Temperature:
This panel provides a read-out of three different temperatures in the ADC1xDxxxx(RF)RB.
21
SNAU146 – September 2013
ADC1xDxxxx(RF)RB Reference Board
Copyright © 2013, Texas Instruments Incorporated