Quick Start
Figure 12. The top level of the Register panel showing the available tabs
The following is a short description of each tab under the
Register
panel.
Settings:
This tab gives choice of either External Clock or Internal Clock, and buttons to initiate FPGA
Reset, Reset Registers and Calibrate ADC. Calibration of the ADC should be performed if changes occur
such as device temperature, mode changes (single channel to dual channel, single edge sampling (Non-
DES) to double edge sampling (DES). For more information, refer to the Calibration section of the
ADC12D1X00RF datasheet. The H/W Trigger function is also enabled using the check box on this tab.
Note:
If the Internal Clock is selected, then the External Clock signal generator should be disconnected or
switched off to prevent performance degradation.
Config:
This tab configures various features and modes of the ADC12D1X00RF and is shown below. It
accesses or changes the following functions, all of which are controlled through Configuration Register 1.
15
SNAU146 – September 2013
ADC1xDxxxx(RF)RB Reference Board
Copyright © 2013, Texas Instruments Incorporated