Texas Instruments ADC1 D (RF )RB Series, User Manual, Page: 16 / 34

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Figure 13. Config Panel
• DPS – DDR Phase Select –
– In DDR, this determines the DDR Data-to-DCLK phase relationship. When unchecked, the 0º Mode
is selected. When checked the 90º Mode is selected.
– In SDR, when this box is unchecked data transitions on the Rising edge of DCLK and when
checked data transitions on the Falling edge of DCLK.
• OVS – Output Voltage Select – Selects the LVDS differential output voltage. When this is unchecked,
the reduced output amplitude is selected. When checked, the standard (higher) output amplitude is
used.
• TPM – Test Pattern Mode – When checked the device will continually output a fixed pattern on the
Data and OR outputs. When cleared, the normal ADC Data and OR information are output.
• PDI – Power down I Channel when checked.
• PDQ – Power down Q channel when checked.
• 2SC – Two’s Complement output mode is selected when checked. Default is offset binary.
• TSE – Check to enable Time Stamp feature.
• SDR – SDR mode when checked; DDR when unchecked. Default is DDR.
Note: Will only work in DDR mode, unless FPGA is changed.
Note: No changes will take effect until the Write Config Reg button is clicked.
Cal Adjust: This tab controls the various adjustments which may be made to the Calibration feature.
16 ADC1xDxxxx(RF)RB Reference Board SNAU146 – September 2013
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