TPCE636 User Manual Issue 1.0.2
Page 69 of 104
TPCE636 DAC Channel LOAD_DAC Register Decoding.
ADR0
'LDAC00_01'
'LDAC02_03'
'LDAC04_05'
'LDAC06_07'
DAC Channel
0
1
0
0
0
Channel 0
1
1
0
0
0
Channel 1
0
0
1
0
0
Channel 2
1
0
1
0
0
Channel 3
0
0
0
1
0
Channel 4
1
0
0
1
0
Channel 5
0
0
0
0
1
Channel 6
1
0
0
0
1
Channel 7
ADR1
'LDAC09_09'
'LDAC10_11'
'LDAC12_13'
'LDAC14_15'
DAC Channel
0
1
0
0
0
Channel 8
1
1
0
0
0
Channel 9
0
0
1
0
0
Channel 10
1
0
1
0
0
Channel 11
0
0
0
1
0
Channel 12
1
0
0
1
0
Channel 13
0
0
0
0
1
Channel 14
1
0
0
0
1
Channel 15
A detailed description of the AD5547 parallel interface and the AD5547 function please use the data sheet
which describes the whole data transfer, data register and output process and all special characteristics of
the DAC.
7.10.4 Output Voltage Range
The output voltage ranges of the TPCE636 DAC outputs are set via
DAC Control / Status Register
and
DAC
Output Voltage Range Register
.
There are three predefined output voltage ranges
±
10V,
±
5V,
±
2,5V and a fourth mode in which the high and
low voltage range can be set individually.
The first three predefined fixed voltage ranges were calibrated as part of the TEWS factory test. Determined
correction values were stored in an I2C EEPROM. There are no correction values for the individually
adjustable voltage range mode.
Due to tolerances of the reference voltage generation, basic tolerances of the DAC components and
temperature dependence, it may happen that the limits for the output voltage cannot be reached.
