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Tews Technologies TPCE636, User Manual

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Tews Technologies TPCE636 User Manual Download Page 65

TPCE636 User Manual Issue 1.0.2 

Page 65 of 104 

Parallel DAC Interface

7.10

7.10.1 Overview

The  16  analog  DAC  outputs  of  the  TPCE636  are  realized  with  eight  AD5547  16bit  Dual-Current  DAC 
devices. Each of these DACs has two DAC channels. Thus, a total of 16 DAC channels are available on the 
TPCE636. Because of current output DACs it is necessary to use operational amplifier for each DAC output 
channel to generate an output voltage range up to ±10V. 

Figure 7-10 :  Analog Output Section 

As  programming  interface,  a  16bit  parallel  Bus  is  implemented.  Respectively  four  DAC  devices  (8  DAC 
channels) share this Kintex-7 16bit data bus. To set each output individually each DAC device has its control 
interface.  

The  following  figure  shows  the  structure  and  principle  of  two  DAC  outputs.  Both  are  connected  via 
independent operational amplifiers to the TPCE636 I/O Connector. 

Figure 7-11 :  Analog Output Section 

The key-features of the TPCE636 DAC Interface are: 

 

16bit Resolution 

 

Built-in 4-quadrant resistors in combination with an operational amplifier allow ±10V outputs 

 

Outputs Drive 

±

10mA per channel 

 

Capacitive Load Driving = 1000pF 

Summary of Contents for TPCE636

Page 1: ...PGA with 16x 16bit Analog Input and 16x 16bit Analog Output Version 1 0 User Manual Issue 1 0 2 January 2019 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek Germany Phone 49 0 4101 4058 0 Fax 49...

Page 2: ...H has made any effort to ensure that this manual is accurate and complete However TEWS TECHNOLOGIES GmbH reserves the right to change the product described in this document at any time without notice...

Page 3: ...Date 1 0 0 First Issue July 2018 1 0 1 Chapter On Board Indicators added to the manual Correction and extension of the JTAG chain description August 2018 1 0 2 Correction of the Electrical Interface...

Page 4: ...2 3 User FPGA JTAG TMS Data Register 0x88 24 5 2 4 User FPGA JTAG TDI Data Register 0x8C 24 5 2 5 User FPGA JTAG TDO Data Register 0x90 25 5 2 6 I2C Bridge Register 0xA0 25 5 2 7 Interrupt Enable Reg...

Page 5: ...7 8 3 1 I2C Calibration Data 56 7 8 3 2 ADC and DAC Calibration Data Values 56 7 8 3 3 DAC Calibration Data Values 57 7 8 3 4 ADC Data Correction Formula 58 7 8 3 5 DAC Data Correction Formula 58 Seri...

Page 6: ...0 FIGURE 7 1 FPGA BLOCK DIAGRAM 33 FIGURE 7 2 MGT BLOCK DIAGRAM 35 FIGURE 7 3 USER JTAG CHAIN 41 FIGURE 7 4 TEWS FACTORY JTAG CHAIN 41 FIGURE 7 5 FPGA CLOCK SOURCES 47 FIGURE 7 6 ANALOG INPUT SECTION...

Page 7: ...LE REGISTER 25 TABLE 5 12 INTERRUPT STATUS REGISTER 26 TABLE 5 13 USER FPGA CONFIGURATION CONTROL STATUS REGISTER 26 TABLE 5 14 USER FPGA CONFIGURATION DATA REGISTER 27 TABLE 5 15 ISP CONTROL REGISTER...

Page 8: ...BOARD STATUS AND USER LEDS 73 TABLE 7 20 TPCE636 USER ON BOARD INDICATORS 74 TABLE 7 21 USER FPGA RESET INPUTS 74 TABLE 9 1 DIFFERENTIAL INPUT VOLTAGE RANGES 76 TABLE 9 2 DAC ELECTRICAL INTERFACE 77...

Page 9: ...nes can be configured as 64 single ended LVCMOS25 lines or as 32 differential LVDS25 lines The User FPGA is connected to a 1GB 32bit wide DDR3 SDRAM The SDRAM interface uses an internal Memory Control...

Page 10: ...2323IUFD 16 Linear Technologies DAC AD5547BRUZ Analog Devices I O Interface Number of analog Input 16 differential 16bit Inputs Analog Input Voltage diff VINMAX allowed voltage between input pins Comm...

Page 11: ...lation according to MIL HDBK 217F and MIL HDBK 217F Notice 2 Environment GB 20 C The MTBF calculation is based on component FIT rates provided by the component suppliers If FIT rates are not available...

Page 12: ...is sensitive to static electricity Packing unpacking and all other handling of the TPCE636 has to be done in an ESD EOS protected Area Thermal Considerations 3 2 Forced air cooling is recommended duri...

Page 13: ...nnector communicating with the host system P15 XC7KxxxT 2 PCIe to PCI Bridge x4 PCIe x1 PCIe x4 PCIe PI7C9X2G312GP XIO2001 LCMXO2 User FPGA Board Configuration Controller FPGA Figure 4 1 PCIe PCI Devi...

Page 14: ...Local Address Space 1 Y FFFFFF00 0x18 PCI Base Address 2 for Local Address Space 2 N 00000000 0x1C PCI Base Address 3 for Local Address Space 3 N 00000000 0x20 PCI Base Address 4 for Local Address Spa...

Page 15: ...F and VREF of DAC Channel 10 32 0x38 Register for VOFF and VREF of DAC Channel 11 32 0x3C Register for VOFF and VREF of DAC Channel 12 32 0x40 Register for VOFF and VREF of DAC Channel 13 32 0x44 Regi...

Page 16: ...bits the value is undefined Reserved register bits shall be written as 0 4 2 2 2 In System Programming Data Space The In System Programming ISP Data Space is used for passing user FPGA configuration d...

Page 17: ...TPCE636 User Manual Issue 1 0 2 Page 17 of 104 5 Register Description User FPGA Kintex 7 5 1 The FPGA register description depends on the user application and is not part of this specification...

Page 18: ...lue 31 16 Reserved R 0 15 14 Reserved R 0 13 DAC2_OUTP_UPD Bits correspond to DAC 1 Refer description for DAC 1 12 DAC2_CLR 11 DAC2_OVRTMP 10 9 DAC2_OUTPSTTLE 8 DAC2_IOBSY 7 6 Reserved R 0 5 DAC1_OUTP...

Page 19: ...16 00 10V range default value 01 5V range 10 2 5V range 11 individual range selection R W 0b00 1 0 REF_DAC1 DAC Output Voltage range selection for DAC channel 1 00 10V range default value 01 5V range...

Page 20: ...which the reference voltage and thus the output voltage range of the TPCE636 can be set Ref DAC LTC2668 Channel 1 DAC AD5547 Channel 2 Ref DAC LTC2668 VREF VREF VOFF VOFF Op Amp Op Amp Front I O Figur...

Page 21: ...llows Vrange_high 1 VOFF Vrange_low 1 VOFF 2 VREF See the following Examples for VOFF VREF Vrange_low Vrange_high Voltage Range Note 10V 0xFFFF 10V 0x0000 10V 10V 10V 10V typical range 5V 0xC000 5V 0x...

Page 22: ...ternal Internal Indicates whether a JTAG device is detected present at the Debug Connector or not 0b0 Device detected present 0b1 No device detected Detection is based on the Debug Connector Present s...

Page 23: ...Vector I O operation Default value causes 256 full clock cycles rising and falling edges to be emitted on TCK r w 0xFF 15 14 Reserved 0 13 JTAG_VIO_SHIFT_ REQ JTAG Vector I O Shift Request Initiates a...

Page 24: ...0b1 Bit I O enabled r w 0 Table 5 6 User FPGA JTAG Signal Line Register 5 2 3 User FPGA JTAG TMS Data Register 0x88 Bit Symbol Description Access Reset Value 31 0 JTAG_VIO_TMS _DATA JTAG Vector I O T...

Page 25: ...Controls the USER I2C Bus BCC reach through onto the management I2C Bus 0 disabled 1 enabled r w 0 Table 5 10 I2C Bridge Register 5 2 7 Interrupt Enable Register 0xC0 Bit Symbol Description Access Res...

Page 26: ..._ENA 1 Kintex 7 to PCIe Switch LINK is enabled 0 Kintex 7 to PCIe Switch LINK is disabled R W 1 3 FP_INIT_STAT User FPGA INIT_B Pin Status 0 FPGA INIT_B Pin Level is Low active 1 FPGA INIT_B Pin Level...

Page 27: ...ser FPGA Slave Select Map Configuration directly to the User FPGA 5 2 11 ISP Control Register 0xE0 Bit Symbol Description Access Reset Value 31 1 Reserved 0 0 ISP_EN ISP Mode Enable 0 Disable ISP Mode...

Page 28: ...t Symbol Description Access Reset Value 31 2 Reserved 0 1 ISP_SPI_RST_CMD ISP SPI Reset Command Bit Writing a 1 sets the Instruction Busy Bit in the ISP Status Register if not already set Breaks any I...

Page 29: ...event based interrupt 0 No ISP SPI Instruction in Progress 1 ISP SPI Instruction in Progress R 0 0 ISP_SPI_ DAT_BSY ISP SPI Data Transfer Busy Status Set Cleared automatically by HW Does not include S...

Page 30: ...ture Data Measured data of the on board temperature sensor The read value of the temperature sensor is stored sign extended as a 8bit two s complement To actually calculate the temperature from the tw...

Page 31: ...CODE_VER The value shows the BCC Firmware code version of the TPCE636 module R Table 5 21 BCC FPGA Code Version Example 0x0100_0A00 bit 32 downto 24 Major FPGA Code Version 0x0100_0A00 bit 23 downto...

Page 32: ...PI Instruction Done Event Interrupt Event based interrupt that becomes active when the ISP SPI Instruction Busy status bit changes from busy to not busy ISP SPI Page Data Done Event Interrupt Event ba...

Page 33: ...ion DAC Interface Back I O ADC Interface VCCO 2 5V VCCO 1 35V VCCO 3 3V PCI Express P16 MGTs 15 VCCO 3 3V DAC Interface PCIe Switch SPI Flash FPGA Conf Data Analog Output 16 x single DAC FIreFly Back...

Page 34: ...igital Converter On chip temperature 4 C max error and power supply 1 max error sensors Continuous JTAG access to ADC measurements Internal access to all internal sensors of the Kintex 7 The board sup...

Page 35: ...ly I O MGT Bank 115 Figure 7 2 MGT Block Diagram MGT TPCE636 Signal FPGA Pins Connected to MGTXTXP0_115 MGTTX0 P2 P1 connected to Back I O FireFly Connector MGTRX0 R4 R3 MGTXTXP1_115 MGTTX1 M2 M1 MGTR...

Page 36: ...lock output of the Si5338 low jitter clock generator MGTREFCLK1_115 and MGTREFCLK1_116 are not used on the TPCE636 MGT TPCE636 Signal FPGA Pins Connected to MGTREFCLK0_115 CLK_MGT H6 H5 156 25 MHz Si5...

Page 37: ...o perform the configuration as quickly as possible The PCIe specification demands that a PCI device must be accessible after 100ms 120ms To speed up the SPI Configuration the following points must be...

Page 38: ...Low FPGA is not configured 1 FPGA DONE Pin Level is High FPGA is configured The link between the PCIe Switch and the Kintex 7 must be enabled A successful User FPGA configuration is indicated with FPG...

Page 39: ...tus Register to 0 Check response of the Kintex 7 by reading the FPGA INIT_B pin value While the FPGA INIT_B pin Level is low the Kintex 7 isn t ready for configuration If FPGA INIT_B pin high then the...

Page 40: ...o the XILINX User Guide ug470 7 Series FPGAs Configuration for more information about Configuration Details and Configuration Data File Formats The following BitGen options are mandatory for the Slave...

Page 41: ...r 7 12 JTAG Controller to K7 JTAG Interface The third option is the USB to JTAG capable FTDI controller which can be accessed via a USB C interface X2 The Molex JTAG connector X5 has default priority...

Page 42: ...nfiguration Register Start the Instruction with ISP Command Register Wait on ISP SPI Instruction Done or ISP SPI Page Data Done for next write instruction Process should be repeated until all configur...

Page 43: ...FPGA is not configured or if it is possible that the FPGA accesses the SPI flash during BCC access set FP_RE_CFG 0b1 Link must be set to disable previously Set the Chip Erase instruction in the ISP C...

Page 44: ...Write the Sector Address to the ISP Configuration Register Set the Chip Erase instruction in the ISP Configuration Register Start the Instruction with ISP Command Register Wait on ISP SPI Instruction...

Page 45: ...ruction in the ISP Configuration Register Start the Instruction with ISP Command Register Wait on ISP SPI Instruction Done or ISP SPI Page Data Done for next write instruction Read one page of SPI Dat...

Page 46: ...rface to BCC Register The TPCE636 BCC provides an I2C Interface to the User FPGA Kintex 7 Via this I2C Interface the TPCE636 Serial Number Register from the BCC Local Configuration Register Space coul...

Page 47: ...clock flow Si514 prog XO Si5338 Clock Generator BCC Kintex 7 DDR3 PCIe Switch Bank 33 32MHz Oscillator 200 MHz REF_CLK 88 889 MHz MCB_CLK 156 25 MHz 100MHz PCIe to PCI 25 MHz PCI CLK 100 MHz User defi...

Page 48: ...Oscillator Differential free I2C prog XO 100kHz up to 250MHz Default 156 MHz SCKOUT_00 Y22 AA22 LTC2323 Diff Clock ADC Ch 0 and 1 SCKOUT_01 AC23 AC24 LTC2323 Diff Clock ADC Ch 2 and 3 SCKOUT_02 Y23 AA...

Page 49: ...open drain buffer The same I2C interface is used for the calibration data prom Si514 I2C Bus Signal Bank VCCO Pin Description Kintex 7 USER_SCL 14 3 3V F25 Serial clock USER_SDA 14 3 3V G26 Serial dat...

Page 50: ...1 IN OUT LVDS_25 BACK_IO2 AE21 IN OUT LVDS_25 BACK_IO3 W20 IN OUT LVDS_25 BACK_IO3 Y21 IN OUT LVDS_25 BACK_IO4 T18 IN OUT LVDS_25 BACK_IO4 T19 IN OUT LVDS_25 BACK_IO5 R16 IN OUT LVDS_25 BACK_IO5 R17 I...

Page 51: ...12 IN OUT LVDS_25 BACK_IO22 B11 IN OUT LVDS_25 BACK_IO23 B14 IN OUT LVDS_25 BACK_IO23 A14 IN OUT LVDS_25 BACK_IO24 C9 IN OUT LVDS_25 BACK_IO24 B9 IN OUT LVDS_25 BACK_IO25 A13 IN OUT LVDS_25 BACK_IO25...

Page 52: ...49 9 VTT P7 A1 A2 AA8 49 9 VTT P3 A2 A3 AF7 49 9 VTT N2 A3 A4 AE7 49 9 VTT P8 A4 A5 W8 49 9 VTT P2 A5 A6 V9 49 9 VTT R8 A6 A7 Y10 49 9 VTT R2 A7 A8 Y11 49 9 VTT T8 A8 A9 Y7 49 9 VTT R3 A9 A10 Y8 49 9...

Page 53: ...ODT E3 DQ0 DQ17 U2 ODT F7 DQ1 DQ18 U1 ODT F2 DQ2 DQ19 V3 ODT F8 DQ3 DQ20 W3 ODT H3 DQ4 DQ21 U7 ODT H8 DQ5 DQ22 V6 ODT G2 DQ6 DQ23 V4 ODT H7 DQ7 DQ24 Y2 ODT D7 DQ8 DQ25 V2 ODT C3 DQ9 DQ26 V1 ODT C8 DQ...

Page 54: ...Device 01 DDR3 Memory Device 02 Both DDR3 Memory Devices 01 02 For details regarding the DDR3 SDRAM interface please refer to XILINX Memory Interface Generator Documentation Xilinx UG586 Zynq 7000 AP...

Page 55: ...Compatible 2 wire Serial EEPROM This EEPROM is used as ADC and DAC calibration data source During factory test the analog input channel gain error and offset error are determined For each device 16bi...

Page 56: ...ror from the reading DAC Gain Error The gain error is the difference between the ideal gain and the actual gain of the DAC It is corrected by multiplying the DAC data value with a correction factor AD...

Page 57: ...Range 10 Channel 16 Gaincorr High Byte 8 0x07F DAC Range 10 Channel 16 Gaincorr Low Byte 8 0x080 DAC Range 5 Channel 1 Offsetcorr High Byte 8 0x081 DAC Range 5 Channel 1 Offsetcorr High Byte 8 0x082 D...

Page 58: ...2767 For higher accuracy they are scaled to LSB Floating point arithmetic or scaled integer arithmetic is necessary to avoid rounding error while computing above formula 7 8 3 5 DAC Data Correction Fo...

Page 59: ...nput voltage on each input pin 20V differential voltage range two stage input operational amplifiers for input impedance conversion and gain adaption are used in addition to the ADC The following figu...

Page 60: ...es the range of ground related voltages that can be tied to the ADC differential inputs This results in an extended input voltage range since the ADC measures the voltage between the differential inpu...

Page 61: ...B26 Convert Signal for ADC Channel 0 and 1 Signal Bank VCCO Pin Description ADC_SCK_01 12 2 5V AF24 Differential Clock Output for ADC Channel 2 and 3 ADC_SCK_01 12 2 5V AF25 ADC_SCKOUT_01 12 2 5V AC23...

Page 62: ...SCK_04 13 2 5V P18 ADC_SCKOUT_04 13 2 5V R22 Differential Clock Input for ADC Channel 8 and 9 ADC_SCKOUT_04 13 2 5V R23 ADC_SDO1_04 13 2 5V T22 Differential Data from ADC Channel 8 ADC_SDO1_04 13 2 5V...

Page 63: ...12 and 13 Signal Bank VCCO Pin Description ADC_SCK_07 13 2 5V T24 Differential Clock Output for ADC Channel 14 and 15 ADC_SCK_07 13 2 5V T25 ADC_SCKOUT_07 13 2 5V P23 Differential Clock Input for ADC...

Page 64: ...sion is triggered by a negative edge on the CNV line The acquisition is done during the positive phase of the CNV signal Following the FPGA drives the SCK clock which then initiates the data transfer...

Page 65: ...0 Analog Output Section As programming interface a 16bit parallel Bus is implemented Respectively four DAC devices 8 DAC channels share this Kintex 7 16bit data bus To set each output individually eac...

Page 66: ...DAC_D11 15 3 3V C16 DAC_D12 15 3 3V C18 DAC_D13 15 3 3V B16 DAC_D14 15 3 3V B19 DAC_D15 15 3 3V A17 DAC_ADR0 15 3 3V E16 DAC Address Line to select the DAC channel A or B from one DAC Device DAC_ WR00...

Page 67: ...ice DAC_ WR08_09 15 3 3V L19 A low active WR transfers data to DAC input register One write signal for each DAC device respectively for two DAC channel DAC_ WR10_11 15 3 3V H19 DAC_ WR12_13 15 3 3V K1...

Page 68: ...hannel 0 0 1 1 1 Channel 0 1 0 1 1 1 Channel 1 0 1 0 1 1 Channel 2 1 1 0 1 1 Channel 3 0 1 1 0 1 Channel 4 1 1 1 0 1 Channel 5 0 1 1 1 0 Channel 6 1 1 1 1 0 Channel 7 ADR1 WR08_09 WR10_11 WR12_13 WR14...

Page 69: ...ch describes the whole data transfer data register and output process and all special characteristics of the DAC 7 10 4 Output Voltage Range The output voltage ranges of the TPCE636 DAC outputs are se...

Page 70: ...e Kintex 7 VCCO voltage for these pins is set to 2 5V so only the 2 5V I O standards LVCMOS25 LVTTL25 and LVDS25 are possible when using the TPCE636 FireFly Back I O interface Signal Name Bank VCCO Pi...

Page 71: ...n the JTAG interface Shift operations require the transfer length JTAG_VIO_XFER_LEN information The value has to be set in accordance to the size of the TMS TDI data vectors or TDO read size and defin...

Page 72: ...resses Note that the Automatic Temperature Read Mode TMP441_AUTO_TRD_EN must be disabled before the bridge mode can be enabled BCC Kintex 7 I2C Bridge Si5338 Clock Generator Bank 15 FPGA I2C BCC I2C T...

Page 73: ...tion on INIT state is active 3 User DONE Green off Device is not configured User FPGA Kintex 7 DONE Pin LED Indicates successful FPGA configuration on Device is completely configured 4 BCC DONE Green...

Page 74: ...l purpose Reset input connected to the User FPGA Kintex 7 Signal Bank VCCO Pin Description DWNRST 14 3 3V K21 Reset from PCIe Switch Based directly on the downstream reset of the PCIe switch on the TP...

Page 75: ...The example design covers the main functionalities of the TPCE636 It implements a PCIe endpoint with interrupt support register mapping DDR3 memory access and basic I O functions It comes as a Xilinx...

Page 76: ...the input voltage range of a differential input one has to differentiate between the differential input voltage between the two pins and the input voltage relative to ground for each pin With an inpu...

Page 77: ...put Interface The output voltage range of each DAC channel can be set via VREF and VOFF See also the chapter about the configuration of the DAC output voltage in the BCC Register Description 9 1 3 Bac...

Page 78: ...TPCE636 User Manual Issue 1 0 2 Page 78 of 104 10 I O Description Overview 10 1...

Page 79: ...4 DAC_OUT1 5 ADC_IN1 6 GND 7 GND 8 GND 9 ADC_IN2 10 DAC_OUT2 11 ADC_IN2 12 GND 13 GND 14 GND 15 ADC_IN3 16 DAC_OUT3 17 ADC_IN3 18 GND 19 GND 20 GND 21 ADC_IN4 22 DAC_OUT4 23 ADC_IN4 24 GND 25 GND 26 G...

Page 80: ...ADC_IN12 70 DAC_OUT12 71 ADC_IN12 72 GND 73 GND 74 GND 75 ADC_IN13 76 DAC_OUT13 77 ADC_IN13 78 GND 79 GND 80 GND 81 ADC_IN14 82 DAC_OUT14 83 ADC_IN14 84 GND 85 GND 86 GND 87 ADC_IN15 88 DAC_OUT15 89 A...

Page 81: ...CK_IO5 b6 BACK_IO5 a7 BACK_IO6 b7 BACK_IO6 a8 BACK_IO7 b8 BACK_IO7 a9 BACK_IO8 b9 BACK_IO8 a10 BACK_IO9 b10 BACK_IO9 a11 BACK_IO10 b11 BACK_IO10 a12 BACK_IO11 b12 BACK_IO11 a13 BACK_IO12 b13 BACK_IO12...

Page 82: ...104 Pin differential I O Pin differential I O a29 BACK_IO28 b29 BACK_IO28 a30 BACK_IO29 b30 BACK_IO29 a31 BACK_IO30 b31 BACK_IO30 a32 BACK_IO31 b32 BACK_IO31 a33 GND b33 GND a34 GND b34 GND Figure 10...

Page 83: ...ector Type Pin Count 38 Connector Type Firefly Micro Flyover Connector Source Order Info Samtec UEC5 019 1 H D RA 2 A Figure 10 2 Firefly Back I O Connector TPCE636 10 4 2 Pin Assignment Pin UEC5 A UE...

Page 84: ...pe Firefly Micro Flyover Connector Source Order Info Samtec UCC8 010 1 H S 2 A Figure 10 4 Firefly Back I O Connector TPCE636 10 4 4 Pin Assignment Pin UCC8 1 3 3V 2 GND 3 PRESENTL 4 SELECTL 5 INTL 6...

Page 85: ...e 2 00 mm Pitch Milli Grid Header Source Order Info Molex 87832 1420 or compatible Figure 10 6 JTAG Header TPCE636 10 5 2 Pin Assignment Pin Signal Description 1 NC Not Connected 2 VREF JTAG Reference...

Page 86: ...tible Source Order Info 632 723 300 011 Figure 10 7 FPGA USB Connector TPCE636 10 6 2 Pin Assignment Pin Description Pin Description A1 A12 B12 B1 USB Typ C A1 GND B12 GND A2 n c B11 n c A3 n c B10 n...

Page 87: ...G3 get_ports PET_N 3 set_property PACKAGE_PIN G4 get_ports PET_P 3 set_property PACKAGE_PIN D1 get_ports PER_N 2 set_property PACKAGE_PIN D2 get_ports PER_P 2 set_property PACKAGE_PIN E3 get_ports PE...

Page 88: ...s DWN_RST_n set_property PULLUP true get_ports DWN_RST_n set_false_path from get_ports DWN_RST_n Section DDR3 DDR3 Data DQ set_property SLEW FAST get_ports DQ 0 set_property IOSTANDARD SSTL135_T_DCI g...

Page 89: ...t_ports DQ 15 set_property SLEW FAST get_ports DQ 16 set_property IOSTANDARD SSTL135_T_DCI get_ports DQ 16 set_property PACKAGE_PIN U5 get_ports DQ 16 set_property SLEW FAST get_ports DQ 17 set_proper...

Page 90: ...35 get_ports A 1 set_property PACKAGE_PIN AA7 get_ports A 1 set_property SLEW FAST get_ports A 2 set_property IOSTANDARD SSTL135 get_ports A 2 set_property PACKAGE_PIN AA8 get_ports A 2 set_property S...

Page 91: ...get_ports RAS_n set_property IOSTANDARD SSTL135 get_ports RAS_n set_property PACKAGE_PIN AA9 get_ports RAS_n DDR3 Column Address Strobe RAS set_property SLEW FAST get_ports CAS_n set_property IOSTAND...

Page 92: ...roperty SLEW FAST get_ports DQS_P 2 set_property IOSTANDARD DIFF_SSTL135_T_DCI get_ports DQS_P 2 set_property SLEW FAST get_ports DQS_N 2 set_property IOSTANDARD DIFF_SSTL135_T_DCI get_ports DQS_N 2 s...

Page 93: ...ADC_SCKOUT_P 1 set_property IOSTANDARD LVDS_25 get_ports ADC_SCKOUT_N 1 set_property DIFF_TERM TRUE get_ports ADC_SCKOUT_N 1 set_property PACKAGE_PIN AC24 get_ports ADC_SCKOUT_N 1 set_property PACKAGE...

Page 94: ...orts ADC_SCK_N 3 set_property PACKAGE_PIN AA25 get_ports ADC_SCK_P 3 set_property IOSTANDARD LVDS_25 get_ports ADC_SCKOUT_P 3 set_property DIFF_TERM TRUE get_ports ADC_SCKOUT_P 3 set_property IOSTANDA...

Page 95: ...s ADC_SCK_P 5 External Termination set_property IOSTANDARD LVDS_25 get_ports ADC_SCK_N 5 External Termination set_property PACKAGE_PIN T17 get_ports ADC_SCK_N 5 set_property PACKAGE_PIN U17 get_ports...

Page 96: ...C 7 set_property SLEW FAST get_ports ADC_CNV_n 7 set_property IOSTANDARD LVCMOS25 get_ports ADC_CNV_n 7 set_property PACKAGE_PIN M22 get_ports ADC_CNV_n 7 set_property IOSTANDARD LVDS_25 get_ports ADC...

Page 97: ...DAC_D 6 set_property DRIVE 8 get_ports DAC_D 6 set_property PACKAGE_PIN F20 get_ports DAC_D 6 set_property IOSTANDARD LVCMOS33 get_ports DAC_D 7 set_property SLEW SLOW get_ports DAC_D 7 set_property D...

Page 98: ...C_D 20 set_property IOSTANDARD LVCMOS33 get_ports DAC_D 21 set_property SLEW SLOW get_ports DAC_D 21 set_property DRIVE 8 get_ports DAC_D 21 set_property PACKAGE_PIN J19 get_ports DAC_D 21 set_propert...

Page 99: ...set_property IOSTANDARD LVCMOS33 get_ports DAC_WR00_01_N set_property SLEW SLOW get_ports DAC_WR00_01_N set_property DRIVE 8 get_ports DAC_WR00_01_N set_property PACKAGE_PIN F15 get_ports DAC_WR00_01_...

Page 100: ..._ports DAC_LDAC10_11 set_property DRIVE 8 get_ports DAC_LDAC10_11 set_property PACKAGE_PIN J21 get_ports DAC_LDAC10_11 set_property IOSTANDARD LVCMOS33 get_ports DAC_LDAC12_13 set_property SLEW SLOW g...

Page 101: ...K_IO4_P set_property PACKAGE_PIN T18 get_ports BACK_IO4_P set_property IOSTANDARD LVDS_25 get_ports BACK_IO4_N set_property PACKAGE_PIN T19 get_ports BACK_IO4_N set_property IOSTANDARD LVDS_25 get_por...

Page 102: ...perty IOSTANDARD LVDS_25 get_ports BACK_IO16_P set_property PACKAGE_PIN E13 get_ports BACK_IO16_P set_property IOSTANDARD LVDS_25 get_ports BACK_IO16_N set_property PACKAGE_PIN E12 get_ports BACK_IO16...

Page 103: ...IO27_N set_property IOSTANDARD LVDS_25 get_ports BACK_IO28_P set_property PACKAGE_PIN G11 get_ports BACK_IO28_P set_property IOSTANDARD LVDS_25 get_ports BACK_IO28_N set_property PACKAGE_PIN F10 get_p...

Page 104: ...orts USER_SDA set_property SLEW SLOW get_ports USER_SCL set_property DRIVE 4 get_ports USER_SCL set_property IOSTANDARD LVCMOS33 get_ports USER_SCL set_property PACKAGE_PIN F25 get_ports USER_SCL BCC...

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