TPCE636 User Manual Issue 1.0.2
Page 33 of 104
7 Functional Description
User FPGA Block Diagram
7.1
Bank 12, 13, 16
Bank 115, 116
B
a
n
k
0
,
1
4
B
a
n
k
3
2
,
3
3
,
3
4
Kintex-7
XC7K160T
XC7K325T
XC7K410T
D
D
R
3
I
n
te
rf
a
ce
C
o
n
fi
g
u
ra
ti
o
n
&
D
A
C
I
n
te
rf
a
ce
Back I/O & ADC Interface
VCCO = 2.5V
V
C
C
O
=
1
.3
5
V
V
C
C
O
=
3
.3
V
PCI-Express & P16 MGTs
15
VCCO = 3.3V
DAC Interface
PCIe Switch
SPI-Flash
(FPGA Conf. Data)
Analog Output
16 x single DAC
FIreFly
Back I/O
4 x MGT
Analog Input
16 x diff. ADC
DDR3 Device 0
DDR3 Device 1
P14 dig. Back I/O
32 x diff. I/O
or 64 x single I/O
GPIO:
- LEDs
- I2C
- User LEDs
- Debug Header
BCC:
- Select Map
- SPI Conf.
- I2C
Figure 7-1 : FPGA Block Diagram
