TPCE636 User Manual Issue 1.0.2
Page 43 of 104
The source for the User FPGA SPI Configuration Flash data could be the .bin file. This file format can
be created from the .bit file by using the XILINX Vivado software.
7.4.6 Erasing User FPGA SPI Configuration Flash
For Chip Erase of the User FPGA SPI Configuration Flash the
User FPGA Configuration Mode
must be set
to
Master Serial / SPI
and the ISP Mode must be enabled.
-
Enable the ISP Mode in the ISP Mode Enable Register.
-
Assure that User FPGA Configuration Mode is set to SPI Flash. If the
FPGA is not configured or if it is possible that the FPGA accesses the SPI
flash during BCC access set FP_RE_CFG = 0b1. Link must be set to
disable previously!
-
Set the Chip Erase instruction in the ISP Configuration Register.
-
Start the Instruction with ISP Command Register
-
Wait on ISP SPI Instruction Done or ISP SPI Page Data Done for erasing
process end.
-
After completion of the erasing process, the ISP Mode bit should be
cleared to set configuration path to User FPGA or a User FPGA SPI
Configuration Flash programming process could be done.
Set
FP_CFG_MD
= 1
Set
FP_RE_CFG
= 1
Set
ISP_ENA
= 1
Write SPI Instruction to
ISP_SPI_INS
Start Instruction with
ISP_SPI_INS_CMD
= 1
Read ISP Status
Register
Inst. busy ?
yes
no
Set
FP_CFG_MD
= 0
Set
ISP_ENA
= 0
