TPCE636 User Manual Issue 1.0.2
Page 37 of 104
User FPGA Configuration
7.4
The Kintex-7 can be configured by the following interfaces:
Master Serial SPI Flash Configuration Interface
JTAG Interface via FPGA JTAG Connector
PCIe Interface via BCC FPGA Slave Select Map Interface Configuration
The change of the configuration mode is done with a configuration register of the BCC FPGA.
At Power-up, the TPCE636 User FPGA (Kintex-7) always configures via x4 SPI Interface by “Master
Serial / SPI” mode.
At factory default the SPI Flash contains the TEWS example application for the TPCE636 User FPGA
device.
7.4.1 Master Serial SPI Flash Configuration
It is important for User FPGA Configuration via SPI Master Mode that the ISP Mode Enable (ISP_EN) bit is
clear to disable the ISP Mode. This is also the default value after Power Up.
See also Register Description of TPCE636 Configuration Device.
To comply with the PCI-Express specification it is necessary to perform the configuration as quickly as
possible. The PCIe specification demands that a PCI device must be accessible after 100ms (120ms). To
speed up the SPI Configuration the following points must be taken into account for SPI Bitstream generation.
External Clock Master (53.2MHz) should be used.
If external Clock Master is used, also the SPI Falling Edge Option must be used.
SPI Configuration Bus Width should be set to X4.
Xilinx Tandem Configuration Feature could be used for full PCI-Express specification compliance.
Already during PCI-Express IP Core generation this configuration feature must be included. (For
more information see: Xilinx XAPP1179).
If the Tandem Configuration feature is used, the Persist Option is mandatory.
For smaller FPGA content, it is sometimes also possible to comply with the PCI-Express
specification, when only Bitstream Compression is used.
To avoid damage on the BCC or User FPGA (Kintex-7) if Tandem configuration or the Persist
Option is used, the User FPGA must be set into reconfigure Mode by using the “FP_RE_CFG” Bit
of the User FPGA Configuration Control/Status Register before Programming or Clearing the SPI
Flash.
