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Tews Technologies TMVE8240-11, User Manual

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Tews Technologies TMVE8240-11 User Manual Download Page 57

 

 

TVME8240 User Manual Issue 1.2.9 

Page 57 of 70 

9.3 LEDs 

During board reset all LEDs are ON. 

9.3.1  FAIL LED 

The FAIL LED (Red) can be set by software control via the Utility LED Register to indicate a failure 
condition. 

9.3.2  FUSE LED 

The FUSE LED (Red) is set by hardware control if any of the on board resettable fuses triggers. 

There is one resettable fuse for each of the following power supplies: 

•

  IP Slot A/B +5V 

•

  IP Slot C/D +5V 

•

  IP Slot A/B/C/D +12V 

•

  IP Slot A/B/C/D -12V 

•

  VME P2 LAN +12V 

9.3.3  ACT LED 

The ACT (Activity) LED (Green) is set by hardware control if there is any activity on the Local Memory 
bus or PCI bus. 

9.3.4  SYS LED 

The SYS (System Controller) LED (Green) is set by hardware control if the Universe (VME-PCI 
Bridge) is the VME bus System Controller. 

Summary of Contents for TMVE8240-11

Page 1: ...gle Board Computer with IndustryPack Interface Version 1 2 User Manual Issue 1 2 9 December 2009 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek Germany Phone 49 0 4101 4058 0 Fax 49 0 4101 4058...

Page 2: ...TECHNOLOGIES GmbH reserves the right to change the product described in this document at any time without notice TEWS TECHNOLOGIES GmbH is not liable for any damage arising out of the application or...

Page 3: ...ected Memory Flash First Instruction offset Updated Technical Information July 2004 1 6 Changed Clock Ratio Recommendation for the MPC8240 EPIC Int Config Reg Added Memory Flash Types Added Note for 1...

Page 4: ...6 2 12 Abort Switch 16 3 ADDRESS MAPS 17 3 1 Address Map Processor View 17 3 2 Address Map PCI Memory Master View 18 3 3 Address Map PCI I O Master View 19 3 4 Address Map Peripheral Devices Detail 19...

Page 5: ...PCI Target Chip 40 8 1 1 PCI9030 PCI Header 41 8 1 2 Local Configuration Register 42 8 1 3 PCI9030 Configuration EEPROM 43 8 2 IP Interface 45 8 2 1 PCI9030 Local Space Assignment 46 8 2 2 Local Spac...

Page 6: ...l Port B 64 9 5 5 LAN Interface Connector 65 10 INSTALLATION AND USE NOTES 66 10 1 NVRAM Real Time Clock Control 66 11 TECHNICAL INFORMATION 67 11 1 Processor 67 11 2 Memory 67 11 3 Other Devices 67 1...

Page 7: ...Y REGISTER DETAIL 20 TABLE 3 8 CONTROL REGISTER 20 TABLE 3 9 STATUS REGISTER 21 TABLE 3 10 LED REGISTER 22 TABLE 4 1 MPC8240 CONFIGURATION REGISTER SETTINGS 25 TABLE 4 2 I2C EEPROM CONTENT 28 TABLE 5...

Page 8: ...16 BIT 53 TABLE 9 13 LOCAL SPACE 3 ADDRESS MAP IP A D MEMORY SPACE 8 BIT 53 TABLE 10 3 BOOT JUMPER 56 TABLE 10 4 VME SYSTEM CONTROLLER JUMPER 56 TABLE 10 5 VME P1 CONNECTOR 59 TABLE 10 6 VME P2 CONNE...

Page 9: ...d Memory FLASH System Memory 64 Mbyte 64 bit wide Synchronous DRAM LAN Interface 21143 10 100Base TX Ethernet Controller 21143 MII Port LXT970 Fast Ethernet Transceiver for RJ45 10 100Base TX 21143 AU...

Page 10: ...net DEC 21143 Option PCI to IndustryPack Bridge 4 IP Slots PCI to VME Bridge Tundra Universe II P 1 P 2 RJ45 50 pin 50 pin 50 pin 50 pin 4 x 50 pin Flat Cable Connector PCI Local Bus 32 bit 33 MHz 8 8...

Page 11: ...y The TVME8240 provides two banks of FLASH memory Bank 0 consists of two 32 pin PLCC sockets each populated with a 512 K x 8 bit FLASH device for a total of 1 Mbyte 8 bit wide Boot FLASH Bank 1 consis...

Page 12: ...ard control and status functions Please refer to the address map section of this manual for details 2 3 PCI Bus The TVME8240 implements a 32 bit 33 MHz PCI bus The TVME8240 implements the following de...

Page 13: ...I Device 0 Universe II VME PCI Bridge 1 21143 LAN Controller 2 SYM53C875 SCSI Controller 3 PCI Expansion e g PMC span 4 N A Table 2 1 PCI Arbiter Assignment 2 3 2 PCI IDSEL Assignment The MPC8240 CPU...

Page 14: ...panel A 10Base T AUI interface is available at the VME P2 connector Please refer to the 21143 and LXT970 manuals for details 2 6 IP Bus Interface The TVME8240 uses a XC2S100 FPGA Xilinx for the Indust...

Page 15: ...grammable Interrupt Controller EPIC in the serial mode The following interrupt sources are available Serial Interrupt No Edge Level Polarity Interrupt Source 0 Level Low VME Bus Error 1 Edge Low ABORT...

Page 16: ...Bus activity Board Failure FAIL Red User controlled Active Fuse FUSE Red Indicates triggered fuses for IP Interface LAN power supply Table 2 4 Status Indicators All status indicators are ON during a...

Page 17: ...EUMB 0xFD00_0000 0xFDFF_FFFF 16 M PCI MEM Space 0 based 0xFE00_0000 0xFE00_FFFF 64 K PCI I O Space 0 based 0xFE01_0000 0xFE7F_FFFF 8 M 64 K Reserved 0xFE80_0000 0xFEBF_FFFF 4 M PCI I O Space 0 based 0...

Page 18: ...FFFF TOP_DRAM 1 0x3FFF_FFFF 1 G DRAM_SIZE Reserved 0x4000_0000 0x7FFF_FFFF 1 G Reserved 0x8000_0000 0xFCEF_FFFF 2 G 49 M PCI Memory Space 0xFCF0_0000 0xFCF0_0FFF 4 K PCI accessible MPC8240 EUMB 0xFCF0...

Page 19: ...eral Devices Detail Address Start End Size Byte Description 0xFFE0_0000 0xFFE0_1FFF 8 K NVRAM RTC 0xFFE0_2000 0xFFE3_FFFF 256 K 8 K Reserved 0xFFE4_0000 0xFFE4_0003 4 UTILITY REG 0xFFE4_0004 0xFFE7_FF...

Page 20: ...LASH_WE R W 0 0 Memory FLASH Writes Disabled 1 Memory FLASH Writes Enabled 3 BOOT_FLASH_WE R W 0 0 Boot FLASH Writes Disabled 1 Boot FLASH Writes Enabled 4 Reserved Write as 0 Undefined for Reads 5 VM...

Page 21: ...Reads 0 No VME Bus Error Event 1 VME Bus Error Event occurred Writes Write as 1 to clear VME Bus Error Status and or to clear VME Bus Error Interrupt Status This status bit is capable of generating a...

Page 22: ...TVME8240 User Manual Issue 1 2 9 Page 22 of 70 Undefined for Reads 6 Reserved Write as 0 Undefined for Reads 7 LSB Reserved Write as 0 Undefined for Reads Table 3 10 LED Register...

Page 23: ...t until the CONFIG_ADDR port value is changed All of the MPC8240 Configuration Registers are intrinsically little endian Therefore all of the following Configuration Register settings are shown in lit...

Page 24: ...R W Reset_Value 0x14 Peripheral Control Status Register Base Address PCSRBAR 4 R W 0xFCF0_0000 0x30 Expansion ROM Base Address 4 R 0x0000_0000 0x3C Interrupt Line 1 R W Reset_Value 0x3D Interrupt Pin...

Page 25: ...rigger Register 1 R W 0x00 0xC0 Error Enabling Register 1 1 R W Reset_Value 0xC1 Error Detection Register 1 1 R C Status 0xC3 Processor Internal Bus Error Status Register 1 R C Status 0xC4 Error Enabl...

Page 26: ...otes The MEMGO bit in the MCCR1 register offset 0xF0 must not be set until all other memory configuration parameters have been appropriately configured The DLL_RESET bit in the AMBOR register offset 0...

Page 27: ...BBAR 0x4_1020 The mode bit in the GCR must be set for EPIC mixed mode operation 4 2 2 2 EPIC Interrupt Configuration Register EICR Offset from EUMBBAR 0x4_1030 The EICR clock ratio field should be set...

Page 28: ...or TVME8240 0x04 Board Option High Byte 0x05 Board Option Low Byte e g 0x000B for TVME8240 11 0x06 Board Version Major 0x07 Board Version Minor V major minor e g 0x0100 V1 0 0x08 0x0F Factory Reserved...

Page 29: ...wed Writes to the Boot FLASH must be enabled in the Utility Control Register The 8 bit wide socket Boot FLASH must always be installed and provide the board initialization code at the system reset vec...

Page 30: ...r ID RA Read Address RD Read Data SA Sector Address WA Write Address WD Write Data Manufacturer Device Manufacture ID Device ID AMD 29F040B 0x01 0xA4 ST 29F040B 0x20 0xE2 Table 5 2 Boot FLASH Auto Sel...

Page 31: ...board mounted Memory FLASH using four 1 M x16 bit FLASH devices The Memory FLASH address range is 0xFF00_0000 to 0xFF7F_FFFF The Memory FLASH data bus port width is 64 bit For writes to the Memory FL...

Page 32: ...x0_0008 DID Write 4 Base 0x2_AAA8 0x00AA00AA 00AA00A Base 0x1_5550 0x00550055 00550055 Base 0x2_AAA8 0x00A000A0 00A000A0 WA WD Chip Erase 6 Base 0x2_AAA8 0x00AA00AA 00AA00A Base 0x1_5550 0x00550055 00...

Page 33: ...after the 6th cycle Symbols DID Device ID MID Manufacturer ID RA Read Address RD Read Data SA Sector Address WA Write Address WD Write Data Manufacturer Device Manufacturer ID Device ID SST 39VF160 0...

Page 34: ...Reserved Header Latency Cache Line 0x0000_0000 0x10 PCI Base Address 0 Configuration Register I O Mapped 0xFFFF_F001 1 4 Kbyte 0x14 PCI Base Address 1 Configuration Register Memory Mapped 0xFFFF_F000...

Page 35: ...4 Universe II Interrupts The Universe II LINT 4 7 interrupt pins are not used The Universe II LINT 0 3 interrupt pins are used as outputs and are mapped to the serial interrupts no 5 8 of the MPC8240...

Page 36: ...Intel 0x0019_1011 0x04 Status Command 0x0280_0007 0x08 Class Code Revision ID 0x0200_0041 0x0C Reserved Header Latency Cache Line 0x0000_0000 0x10 PCI Base Address 0 Configuration Register I O Mapped...

Page 37: ...inter High 0x0000 0x04 Card bus CIS Pointer Low 0x0000 0x6 ID_Reserved1 0x0000 0x8 ID_Reserved1 0x0000 0xA ID_Reserved1 0x0000 0xC MiscHwOptions ID_Reserved1 0x00 0x00 0xF Func0HwOptions ID_BLOCK_CRC...

Page 38: ...0x2B PHY 0x00 0x2C GPR Seq Length 0x00 0x2D RST Seq Length 0x03 0x2E RST Sequence 1st Word 0x0801 0x2F RST Sequence 2nd Word 0x0000 0x31 RST Sequence 3rd Word 0x0001 0x33 Media Capabilities 0x7800 0x...

Page 39: ...CRC MAC Addr 00_01_06_uv_wx_yz Table 7 3 21143 Configuration EEPROM Content 7 3 21143 Ports The 21143 MII port connects to an Intel LXT970 Fast Ethernet transceiver to build the Fast Ethernet interfa...

Page 40: ...face A FPGA is used on the PCI9030 local bus to build the IP interface and provide IP Interface Control Registers 8 1 PCI9030 PCI Target Chip The PCI9030 provides four local spaces 0 3 that are used f...

Page 41: ...pace 0 0xFFFF_FF00 1 256 Byte 0x1C PCI Base Address 3 PCIBAR3 Local Space 1 0xFFFF_FC00 1 1 Kbyte 0x20 PCI Base Address 4 PCIBAR4 Local Space 2 0xFE00_0000 1 32 Mbyte 0x24 PCI Base Address 5 PCIBAR5 L...

Page 42: ...Space 1 Remap LAS1BA 0x0400_0001 0x1C Local Space 2 Remap LAS2BA 0x0000_0001 0x20 Local Space 3 Remap LAS3BA 0x0200_0001 0x24 Expansion ROM Remap EROMBA 0x0000_0000 0x28 Local Space 0 Descriptor LAS0...

Page 43: ...agement Data PMCSR Bridge Support Ext Reserved 0x0000 0x1E PCI 0x44 LSW Power Management Control Status PMCSR 14 8 0x0000 0x20 PCI 0x4A MSW Hot Swap Control Status Reserved 0x0000 0x22 PCI 0x48 LSW Ho...

Page 44: ...0x20A2 0x60 Local 0x3A MSW Local Exp ROM Descriptor EROMBRD 31 16 0x0000 0x62 Local 0x38 LSW Local Exp ROM Descriptor EROMBRD 15 0 0x0000 0x64 Local 0x3E MSW Local Chip Select 0 CS0BASE 31 16 0x0800 0...

Page 45: ...F 0xFFFF 0xFFFF 0x90 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xA0 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xB0 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0...

Page 46: ...O Space 2 32 M 16 Big Mem IP A D MEM Space 16 bit 3 16 M 8 Big Mem IP A D MEM Space 8 bit Table 8 5 PCI9030 Local Space Assignment 8 2 2 Local Space 0 Address Map The PCI9030 local space 0 is used for...

Page 47: ...3 1 Revision ID Register The Revision ID Register shows the revision of the on board IP FPGA logic Bit Name Description 15 MSB 14 13 12 11 10 9 8 Read Undefined Write No Effect 7 6 5 4 3 2 1 0 LSB REV...

Page 48: ...terrupt 1 Level Sensitive 1 IP Interrupt 1 Edge Sensitive 4 INT0_SENSE 0 IP Interrupt 0 Level Sensitive 1 IP Interrupt 0 Edge Sensitive 3 ERR_INT_EN 0 IP Error Interrupt Disabled 1 IP Error Interrupt...

Page 49: ...al is negated Bit Name Description 15 MSB 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Read Undefined Write No Effect Should be written with 0 s 0 LSB IP_RESET Read 0 IP RESET Signal is De asserted 1 IP RESET Sig...

Page 50: ...Timeout on IP_D 1 IP_D Timeout has occurred Write 0 No Effect 1 Clear IP_D Timeout Status 14 TIME_C Read 0 No Timeout on IP_C 1 IP_C Timeout has occurred Write 0 No Effect 1 Clear IP_C Timeout Status...

Page 51: ...C 1 Active IP_C Interrupt 1 Request Write 0 No Effect 1 Clear Edge Sensitive IP_C Interrupt 1 Status 4 INT0_C Read 0 No Interrupt 0 Request on IP_C 1 Active IP_C Interrupt 0 Request Write 0 No Effect...

Page 52: ...x0000_017F 128 IP B I O Space 0x0000_0180 0x0000_01BF 64 IP B ID Space 0x0000_01C0 0x0000_01FF 64 IP B INT Space 0x0000_0200 0x0000_027F 128 IP C I O Space 0x0000_0280 0x0000_02BF 64 IP C ID Space 0x0...

Page 53: ...able 8 12 Local Space 2 Address Map IP A D Memory Space 16 bit 8 2 6 Local Space 3 Address Map The PCI9030 local space 3 is used for the IP A D Memory space 8 bit port The PCI base address for local s...

Page 54: ...nputs to its PCI interrupt output INTA The PCI9030 PCI interrupt output is mapped to the serial interrupt no 4 of the MPC8240 EPIC The PCI9030 local interrupt 2 LINT2 is not used Upon detecting EPIC S...

Page 55: ...TVME8240 User Manual Issue 1 2 9 Page 55 of 70 9 Board I O 9 1 Board I O Overview Figure 9 1 Board I O Overview...

Page 56: ...wide socket Boot FLASH must always be installed and provide the board initialization code at the system reset vector If used the first instruction in the Memory FLASH must reside at address 0xFF00_01...

Page 57: ...if any of the on board resettable fuses triggers There is one resettable fuse for each of the following power supplies IP Slot A B 5V IP Slot C D 5V IP Slot A B C D 12V IP Slot A B C D 12V VME P2 LAN...

Page 58: ...ity Control Register A board reset will perform a general board hardware reset re configuration of the IP FPGA PCI reset and CPU reset If the TVME8240 is the VME bus system controller a board reset wi...

Page 59: ...BGIN3 VME_SYSFAIL 11 GND VME_BGOUT3 VME_BERR 12 VME_DS1 VME_BR0 VME_SYSRST 13 VME_DS0 VME_BR1 VME_LWORD 14 VME_WRITE VME_BR2 VME_AM5 15 GND VME_BR3 VME_A23 16 VME_DTACK VME_AM0 VME_A22 17 GND VME_AM1...

Page 60: ...nector Please see the SCSI Interface section for using 16bit SCSI Targets on the VME P2 connector Pin Row A Row B Row C 1 SCSI_D0 5V AUI_CD 2 SCSI_D1 GND AUI_CD 3 SCSI_D2 NC AUI_TD 4 SCSI_D3 VME_A24 A...

Page 61: ...EL 34 DMAACK 35 IOSEL 36 RSV0 37 A1 38 DMAEND 39 A2 40 ERROR 41 A3 42 INTREQ0 43 A4 44 INTREQ1 45 A5 46 STROBE 47 A6 48 ACK 49 RSV1 50 GND Table 9 5 IP P1 Connector The following signals have an on bo...

Page 62: ...K 24 SDONE 25 DEVSEL 26 SBO 27 GND 28 GND 29 TRDY 30 IRDY 31 STOP 32 FRAME 33 GND 34 GND 35 ACK64 36 NC 37 REQ64 38 NC 39 PAR 40 RST 41 C BE1 42 C BE0 43 C BE3 44 C BE2 45 AD1 46 AD0 47 AD3 48 AD2 49...

Page 63: ...36 89 AD39 90 AD38 91 AD41 92 AD40 93 AD43 94 AD42 95 AD45 GND 96 AD44 97 AD47 98 AD46 99 AD49 100 AD48 101 AD51 102 AD50 103 AD53 104 AD52 105 AD55 106 AD54 107 AD57 108 AD56 109 AD59 110 AD58 111 AD...

Page 64: ...input 7 RTS output 8 CTS input 9 RI input Table 9 7 Serial Port A DB9 male Connector 9 5 4 2 Serial Port B RS232 Adapter TVME8240 A1 10 The RS232 adapter card TVME824 A1 10 will be delivered with ever...

Page 65: ...nal TXD line must be connected to pin 2 RXD input of the serial port A connector not to pin 3 TXD output The serial interface signals are also available on the VME P2 connector For each serial port on...

Page 66: ...48T59 NVRAM device The Real Time Clock function of the M48T59 device is turned off by default to save battery energy If the M48T59 Real Time Clock function has been turned off factory default it must...

Page 67: ...Memory 11 3 Other Devices 8 Kbyte NVRAM M48T59 with exchangeable battery 1 Mbyte 8 bit wide Boot Flash two PLCC sockets 11 4 VME Interface Tundra Universe II A16 A32 Master Slave Address Modes D08 D64...

Page 68: ...r 5V PCI signal levels PCI Expansion Board must tolerate 5V PCI signal levels Supports Motorola PMC Span TEWS IP Span TVME230 11 8 Power Requirements The TVME8240 uses the 5V 12V and 12V power supply...

Page 69: ...VME P1 and P2 connectors are rated for 2A max 20 C appr 1 5A max 70 C per pin For the 5V power supply there are 3 pins on the VME P1 connector and 3 pins on the VME P2 connector For the 12V power supp...

Page 70: ...1 MTBF Data 11 10 2 Temperature Operating Temperature Range 0 C to 55 C forced air cooling Non Operating Temperature Range 40 C to 85 C 11 10 3 Weight TVME8240 11 372 5 g 11 10 4 Humidity 5 to 90 non...

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