TVME8240 User Manual Issue 1.2.9
Page 50 of 70
8.2.3.4 Status Register
The Status Register can be used to read IP timeout, error and interrupt status.
The IP timeout time is app. 8µs.
An IP timeout occurs if the IP module fails to generate the IP ACK# signal within the IP timeout
time. An IP timeout is not reported to the PCI9030 or the PCI Master, but in the Status Register.
For timeout reads all F's are returned.
Bit
Name
Description
15
(MSB)
TIME_D
Read :
0 : No Timeout on IP_D
1 : IP_D Timeout has occurred
Write :
0 : No Effect
1 : Clear IP_D Timeout Status
14 TIME_C
Read :
0 : No Timeout on IP_C
1 : IP_C Timeout has occurred
Write :
0 : No Effect
1 : Clear IP_C Timeout Status
13 TIME_B
Read :
0 : No Timeout on IP_B
1 : IP_B Timeout has occurred
Write :
0 : No Effect
1 : Clear IP_B Timeout Status
12 TIME_A
Read :
0 : No Timeout on IP_A
1 : IP_A Timeout has occurred
Write :
0 : No Effect
1 : Clear IP_A Timeout Status
11 ERR_D
Read :
0 : No Error on IP_D
1 : IP_D ERROR# Signal Asserted
Write :
No Effect
10 ERR_C
Read :
0 : No Error on IP_C
1 : IP_C ERROR# Signal Asserted
Write :
No Effect
9 ERR_B
Read :
0 : No Error on IP_B
1 : IP_B ERROR# Signal Asserted
Write :
No Effect
