TVME8240 User Manual Issue 1.2.9
Page 23 of 70
4 MPC8240
The TVME8240 uses the MPC8240 in host mode with address map B.
The MPC8240 processor and peripheral logic are configured to operate in big endian mode.
4.1 MPC8240 Configuration Register
Setting up the MPC8240 Configuration Registers is scope of the board initialization software.
4.1.1 Configuration Register Access
The MPC8240 Configuration Registers are accessed in two steps:
1.
A 32 bit register address 0x8000_00nn is written to the CONFIG_ADDR port at 0xFEC0_0000,
where nn is the (word-aligned) register offset.
2.
Data is accessed at the CONFIG_DATA port at 0xFEE0_000m, where m is the offset within the
word-aligned address (depending on transfer size).
Data can be accessed multiple times at the CONFIG_DATA port until the CONFIG_ADDR port value
is changed.
All of the MPC8240 Configuration Registers are intrinsically little endian. Therefore all of the following
Configuration Register settings are shown in little endian order.
Since on the TVME8240 the MPC8240 processor and peripheral logic operates in big endian mode,
software must either use byte reversed load / store instructions or byte-swap the values for the
CONFIG_ADDR and CONFIG_DATA port access.
E.g. for reading the Device ID Register (offset 0x02) one should write 0x0000_0080 (0x00 is the word-
aligned offset for 0x02) to 0xFEC0_0000 and read the half-word 0x0300 at 0xFEE0_0002.
E.g. for setting the Output Driver Control Register (offset 0x73) one should write 0x7000_0080 (0x70
is the word-aligned offset for 0x73) to 0xFEC0_0000 and write the byte 0xC0 to 0xFEE0_0003.
E.g. for setting the EUMBBAR Register (offset 0x78) to 0xFCF0_0000 one should write 0x78000080
to 0xFEC0_0000 and write the word 0x0000F0FC to 0xFEE0_0000.
