Tews Technologies TMVE8240-11, User Manual

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TVME8240 User Manual Issue 1.2.9 Page 19 of 70
3.3 Address Map – PCI I/O Master View
PCI I/O Address
Start End
Size
(Byte)
Description
0x0000_0000 0x0000_FFFF 64 K PCI I/O Space
0x0001_0000 0x007F_FFFF 8 M – 64 K Reserved
0x0080_0000 0x00BF_FFFF 4 M PCI I/O Space
0x00C0_0000 0xFFFF_FFFF 4 G – 12 M Reserved
Table 3-5 : Address Map – PCI I/O Master View
The MPC8240 does not responding as a target to PCI I/O cycles.
3.4 Address Map – Peripheral Devices Detail
Address
Start End
Size
(Byte)
Description
0xFFE0_0000 0xFFE0_1FFF 8 K NVRAM / RTC
0xFFE0_2000 0xFFE3_FFFF 256 K – 8 K Reserved
0xFFE4_0000 0xFFE4_0003 4 UTILITY REG
0xFFE4_0004 0xFFE7_FFFF 256 K – 4 Reserved
0xFFE8_0000 0xFFE8_0007 8 UART CH A
0xFFE8_0008 0xFFE8_000F 8 UART CH B
0xFFE8_0010 0xFFEF_FFFF 512 K -16 Reserved
Table 3-6 : Address Map – Peripheral Devices Detail
For read or write accesses to the Peripheral Devices only 8 bit (byte) transfer sizes are allowed.
For the NVRAM / RTC register map please refer to the M48T59 device documentation.
For the UART register map please refer to the XR16C2550 documentation.