TVME8240 User Manual Issue 1.2.9
Page 54 of 70
8.3 IP Interrupts
The IP FPGA maps all IP interface interrupts sources (Timeout, Error, INT0, INT1) to the PCI9030
local interrupt input 1 (LINT1#).
The PCI9030 PCI Target Chip maps its local interrupt inputs to its PCI interrupt output (INTA#).
The PCI9030 PCI interrupt output is mapped to the serial interrupt no. 4 of the MPC8240 EPIC.
The PCI9030 local interrupt 2 (LINT2#) is not used.
Upon detecting EPIC Serial Interrupt No. 4 read the IP Status Register to determine the IP interrupt
source.
Timeout interrupts and edge sensitive IP interrupts must be cleared in the IP Status Register.
Error interrupts should be disabled after being noticed once.
