Terasic DE10-Standard Page 90 User Manual Download

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DE10-Standard
User Manual

www.terasic.com

January 19, 2017



Makefile

A Makefile is required to compile a project. The Makefile used for this demo is:



Compile

Please launch SoC EDS Command Shell to compile a project by executing

C:\intelFPGA\16.1\embedded

Embedded_Command_Shell.bat

The "cd" command can change the current directory to where the Hello World project is located.
The "make" command will build the project. The executable file "

my_first_hps

" will be generated

after the compiling process is successful. The "clean all" command removes all temporary files.



Demonstration Source Code



Build tool: SoC EDS v16.1

Summary of Contents for DE10-Standard

Page 1: ...DE10 Standard User Manual 1 www terasic com January 19 2017 ...

Page 2: ...Standard Board 13 3 1 Settings of FPGA Configuration Mode 13 3 2 Configuration of Cyclone V SoC FPGA on DE10 Standard 14 3 3 Board Status Elements 20 3 4 Board Reset Elements 21 3 5 Clock Circuitry 22 3 6 Peripherals Connected to the FPGA 23 3 6 1 User Push buttons Switches and LEDs 23 3 6 2 7 segment Displays 27 3 6 3 2x20 GPIO Expansion Header 28 3 6 4 HSMC connector 30 3 6 5 24 bit Audio CODEC ...

Page 3: ... 52 3 7 8 LTC Connector 53 3 7 9 128x64 Dots LCD 54 Chapter 4 DE10 Standard System Builder 56 4 1 Introduction 56 4 2 Design Flow 56 4 3 Using DE10 Standard System Builder 57 Chapter 5 Examples For FPGA 63 5 1 DE10 Standard Factory Configuration 63 5 2 Audio Recording and Playing 64 5 3 Karaoke Machine 66 5 4 SDRAM Test in Nios II 68 5 5 SDRAM Test in Verilog 71 5 6 TV Box Demonstration 73 5 7 PS ...

Page 4: ...ground 105 7 2 System Requirements 106 7 3 AXI bridges in Intel SoC FPGA 106 7 4 GHRD Project 107 7 5 Compile and Programming 109 7 6 Develop the C Code 110 Chapter 8 Programming the EPCS Device 116 8 1 Before Programming Begins 116 8 2 Convert SOF File to JIC File 116 8 3 Write JIC File into the EPCS Device 121 8 4 Erase the EPCS Device 123 Chapter 9 Appendix 125 9 1 Revision History 125 9 2 Copy...

Page 5: ...processor system Altera s SoC integrates an ARM based hard processor system HPS consisting of processor peripherals and memory interfaces tied seamlessly with the FPGA fabric using a high bandwidth interconnect backbone The DE10 Standard development board is equipped with high speed DDR3 memory video and audio capabilities Ethernet networking and much more that promise many exciting applications T...

Page 6: ... ys st te em m C CD D The DE10 Standard System CD contains all the documents and supporting materials associated with DE10 Standard including the user manual system builder reference designs and device datasheets Users can download this system CD from the link http de10 standard terasic com cd 1 1 3 3 G Ge et tt ti in ng g H He el lp p Here are the addresses where you can get help if you encounter...

Page 7: ...DE10 Standard User Manual 6 www terasic com January 19 2017 ...

Page 8: ...an introduction to the features and design characteristics of the board 2 2 1 1 L La ay yo ou ut t a an nd d C Co om mp po on ne en nt ts s Figure 2 1 shows a photograph of the board It depicts the layout of the board and indicates the location of the connectors and key components Figure 2 1 DE10 Standard development board top view ...

Page 9: ...erial configuration device EPCS128 USB Blaster II onboard for programming JTAG Mode 64MB SDRAM 16 bit data bus 4 push buttons 10 slide switches 10 red user LEDs Six 7 segment displays Four 50MHz clock sources from the clock generator 24 bit CD quality audio CODEC with line in line out and microphone in jacks VGA DAC 8 bit high speed triple DACs with VGA out connector TV decoder NTSC PAL SECAM and ...

Page 10: ...r I2C interface interrupt UART to USB USB Mini B connector Warm reset button and cold reset button One user button and one user LED LTC 2x7 expansion header 128x64 dots LCD Module with Backlight 2 2 2 2 B Bl lo oc ck k D Di ia ag gr ra am m o of f t th he e D DE E1 10 0 S St ta an nd da ar rd d B Bo oa ar rd d Figure 2 3 is the block diagram of the board All the connections are established through...

Page 11: ...n about Figure 2 3 are listed below F FP PG GA A D De ev vi ic ce e Cyclone V SoC 5CSXFC6D6F31C6N Device Dual core ARM Cortex A9 HPS 110K programmable logic elements 5 140 Kbits embedded memory 6 fractional PLLs 2 hard memory controllers 3 125G transceivers C Co on nf fi ig gu ur ra at ti io on n a an nd d D De eb bu ug g ...

Page 12: ... Ethernet PS 2 mouse keyboard IR emitter receiver I2C multiplexer C Co on nn ne ec ct to or rs s One HSMC 8 channel Transceivers Configurable I O standards 1 5 1 8 2 5 3 3V One 40 pin expansion headers One 10 pin ADC input header One LTC connector one Serial Peripheral Interface SPI Master one I2C and one GPIO interface D Di is sp pl la ay y 24 bit VGA DAC 128x64 dots LCD Module with Backlight A A...

Page 13: ...tc ch he es s B Bu ut tt to on ns s a an nd d I In nd di ic ca at to or rs s 5 user Keys FPGA x4 HPS x1 10 user switches FPGA x10 11 user LEDs FPGA x10 HPS x 1 2 HPS reset buttons HPS_RESET_n and HPS_WARM_RST_n Six 7 segment displays S Se en ns so or rs s G Sensor on HPS P Po ow we er r 12V DC input ...

Page 14: ...o on nf fi ig gu ur ra at ti io on n M Mo od de e When the DE10 Standard board is powered on the FPGA can be configured from EPCS or HPS The MSEL 4 0 pins are used to select the configuration scheme It is implemented as a 6 pin DIP switch SW10 on the DE10 Standard board as shown in Figure 3 1 Figure 3 1 DIP switch SW10 setting of Active Serial AS mode on DE10 Standard board Table 3 1 shows the rel...

Page 15: ... 3 2 2 C Co on nf fi ig gu ur ra at ti io on n o of f C Cy yc cl lo on ne e V V S So oC C F FP PG GA A o on n D DE E1 10 0 S St ta an nd da ar rd d There are two types of programming method supported by DE10 Standard 1 JTAG programming It is named after the IEEE standards Joint Test Action Group The configuration bit stream is downloaded directly into the Cyclone V SoC FPGA The FPGA will retain it...

Page 16: ... FPGA device Figure 3 2 illustrates the JTAG chain on DE10 Standard board Figure 3 2 Path of the JTAG chain Configure the FPGA in JTAG Mode There are two devices FPGA and HPS on the JTAG chain The following shows how the FPGA is programmed in JTAG mode step by step 1 Open the Quartus II programmer and click Auto Detect as circled in Figure 3 3 ...

Page 17: ...erasic com January 19 2017 Figure 3 3 Detect FPGA device in JTAG mode 2 Select detected device associated with the board as circled in Figure 3 4 Figure 3 4 Select 5CSXFC6D6 device 3 Both FPGA and HPS are detected as shown in Figure 3 5 ...

Page 18: ...andard User Manual 17 www terasic com January 19 2017 Figure 3 5 FPGA and HPS detected in Quartus programmer 4 Right click on the FPGA device and open the sof file to be programmed as highlighted in Figure 3 6 ...

Page 19: ... www terasic com January 19 2017 Figure 3 6 Open the sof file to be programmed into the FPGA device 5 Select the sof file to be programmed as shown in Figure 3 7 Figure 3 7 Select the sof file to be programmed into the FPGA device ...

Page 20: ...n data is automatically loaded from the quad serial configuration device chip into the FPGA when the board is powered up Users need to use Serial Flash Loader SFL to program the quad serial configuration device via JTAG interface The FPGA based SFL is a soft intellectual property IP core within the FPGA that bridge the JTAG and Flash interfaces The SFL Megafunction is available in Quartus II Figur...

Page 21: ...3 3 3 B Bo oa ar rd d S St ta at tu us s E El le em me en nt ts s In addition to the 10 LEDs that FPGA device can control there are 5 indicators which can indicate the board status See Figure 3 10 please refer the details in Table 3 3 Figure 3 10 LED Indicators on DE10 Standard Table 3 3 LED Indicators Board Reference LED Name Description ...

Page 22: ...eserved D4 JTAG_TX 3 3 4 4 B Bo oa ar rd d R Re es se et t E El le em me en nt ts s There are two HPS reset buttons on DE10 Standard HPS cold reset and HPS warm reset as shown in Figure 3 11 Table 3 4 describes the purpose of these two HPS reset buttons Figure 3 12 is the reset tree for DE10 Standard Figure 3 11 HPS cold reset and warm reset buttons on DE10 Standard Table 3 4 Description of Two HP...

Page 23: ...cu ui it tr ry y Figure 3 13 shows the default frequency of all external clocks to the Cyclone V SoC FPGA A clock generator is used to distribute clock signals with low jitter The four 50MHz clock signals connected to the FPGA are used as clock sources for user logic One 25MHz clock signal is connected to two HPS clock inputs and the other one is connected to the clock input of Gigabit Ethernet Tr...

Page 24: ...ck input 3 3V HPS_CLOCK1_25 PIN_D25 25 MHz clock input 3 3V HPS_CLOCK2_25 PIN_F25 25 MHz clock input 3 3V 3 3 6 6 P Pe er ri ip ph he er ra al ls s C Co on nn ne ec ct te ed d t to o t th he e F FP PG GA A This section describes the interfaces connected to the FPGA Users can control or monitor different interfaces with user logic from the FPGA 3 6 1 User Push buttons Switches and LEDs The board ha...

Page 25: ... inputs in a circuit Figure 3 14 Connections between the push buttons and the Cyclone V SoC FPGA Pushbutton released Pushbutton depressed Before Debouncing Schmitt Trigger Debounced Figure 3 15 Switch debouncing There are ten slide switches connected to the FPGA as shown in Figure 3 16 These switches are not debounced and to be used as level sensitive data inputs to a circuit Each switch is connec...

Page 26: ...lable LEDs connected to the FPGA Each LED is driven directly and individually by the Cyclone V SoC FPGA driving its associated pin to a high logic level or low level to turn the LED on or off respectively Figure 3 17 shows the connections between LEDs and Cyclone V SoC FPGA Table 3 6 Table 3 7 and Table 3 8 list the pin assignment of user push buttons switches and LEDs ...

Page 27: ...P3 SW 4 PIN_W25 Slide Switch 4 Depend on JP3 SW 5 PIN_V25 Slide Switch 5 Depend on JP3 SW 6 PIN_AC28 Slide Switch 6 Depend on JP3 SW 7 PIN_AD30 Slide Switch 7 Depend on JP3 SW 8 PIN_AC29 Slide Switch 8 Depend on JP3 SW 9 PIN_AA30 Slide Switch 9 Depend on JP3 Table 3 7 Pin Assignment of Push buttons Signal Name FPGA Pin No Description I O Standard KEY 0 PIN_AJ4 Push button 0 3 3V KEY 1 PIN_AK4 Push...

Page 28: ...PGA The segment can be turned on or off by applying a low logic level or high logic level from the FPGA respectively Each segment in a display is indexed from 0 to 6 with corresponding positions given in Figure 3 18 Table 3 9 shows the pin assignment of FPGA to the 7 segment displays Figure 3 18 Connections between the 7 segment display HEX0 and the Cyclone V SoC FPGA Table 3 9 Pin Assignment of 7...

Page 29: ...git 3 3 3 3V HEX3 4 PIN_AC20 Seven Segment Digit 3 4 3 3V HEX3 5 PIN_AA19 Seven Segment Digit 3 5 3 3V HEX3 6 PIN_AD20 Seven Segment Digit 3 6 3 3V HEX4 0 PIN_AD21 Seven Segment Digit 4 0 3 3V HEX4 1 PIN_AG22 Seven Segment Digit 4 1 3 3V HEX4 2 PIN_AE22 Seven Segment Digit 4 2 3 3V HEX4 3 PIN_AE23 Seven Segment Digit 4 3 3 3V HEX4 4 PIN_AG23 Seven Segment Digit 4 4 3 3V HEX4 5 PIN_AF23 Seven Segme...

Page 30: ...n No Description I O Standard GPIO 0 PIN_W15 GPIO Connection 0 0 3 3V GPIO 1 PIN_AK2 GPIO Connection 0 1 3 3V GPIO 2 PIN_Y16 GPIO Connection 0 2 3 3V GPIO 3 PIN_AK3 GPIO Connection 0 3 3 3V GPIO 4 PIN_AJ1 GPIO Connection 0 4 3 3V GPIO 5 PIN_AJ2 GPIO Connection 0 5 3 3V GPIO 6 PIN_AH2 GPIO Connection 0 6 3 3V GPIO 7 PIN_AH3 GPIO Connection 0 7 3 3V GPIO 8 PIN_AH4 GPIO Connection 0 8 3 3V GPIO 9 PIN...

Page 31: ... 0 30 3 3V GPIO 31 PIN_AD12 GPIO Connection 0 31 3 3V GPIO 32 PIN_AC9 GPIO Connection 0 32 3 3V GPIO 33 PIN_AC12 GPIO Connection 0 33 3 3V GPIO 34 PIN_AB12 GPIO Connection 0 34 3 3V GPIO 35 PIN_AA12 GPIO Connection 0 35 3 3V 3 6 4 HSMC connector The board contains a High Speed Mezzanine Card HSMC interface to provide a mechanism for extending the peripheral set of an FPGA host board by means of ad...

Page 32: ...rolled by the header JP3 users can use a jumper to select the input voltage of VCCIO5B VCCIO8A to 3 3V 2 5V 1 8V and 1 5V to control the voltage level of the I O pins Table 3 lists the jumper settings of the JP3 Table 3 shows all the pin assignments of the HSMC connector Table 3 13 Jumper Settings for different I O Standards JP3 Jumper Settings Supplied Voltage to VCCIO5B VCCIO8A IO Voltage of HSM...

Page 33: ... RX bit 0n or CMOS I O Depend on JP3 HSMC_RX_D_N 1 PIN_J12 LVDS RX bit 1n or CMOS I O Depend on JP3 HSMC_RX_D_N 2 PIN_F10 LVDS RX bit 2n or CMOS I O Depend on JP3 HSMC_RX_D_N 3 PIN_J9 LVDS RX bit 3n or CMOS I O Depend on JP3 HSMC_RX_D_N 4 PIN_K8 LVDS RX bit 4n or CMOS I O Depend on JP3 HSMC_RX_D_N 5 PIN_H7 LVDS RX bit 5n or CMOS I O Depend on JP3 HSMC_RX_D_N 6 PIN_G8 LVDS RX bit 6n or CMOS I O Dep...

Page 34: ...TX bit 9n or CMOS I O Depend on JP3 HSMC_TX_D_N 10 PIN_B1 LVDS TX bit 10n or CMOS I O Depend on JP3 HSMC_TX_D_N 11 PIN_A3 LVDS TX bit 11n or CMOS I O Depend on JP3 HSMC_TX_D_N 12 PIN_A5 LVDS TX bit 12n or CMOS I O Depend on JP3 HSMC_TX_D_N 13 PIN_B7 LVDS TX bit 13n or CMOS I O Depend on JP3 HSMC_TX_D_N 14 PIN_B8 LVDS TX bit 14n or CMOS I O Depend on JP3 HSMC_TX_D_N 15 PIN_B11 LVDS TX bit 15n or CM...

Page 35: ...r in the directory datasheets Audio CODEC of DE10 Standard System CD Figure 3 20 Connections between the FPGA and audio CODEC Table 3 14 Pin Assignment of Audio CODEC Signal Name FPGA Pin No Description I O Standard AUD_ADCLRCK PIN_AH29 Audio CODEC ADC LR Clock 3 3V AUD_ADCDAT PIN_AJ29 Audio CODEC ADC Data 3 3V AUD_DACLRCK PIN_AG30 Audio CODEC DAC LR Clock 3 3V AUD_DACDAT PIN_AF29 Audio CODEC DAC ...

Page 36: ...roller 3 3V HPS_I2C2_SCLK PIN_H23 I2C Clock of the second HPS I2C concontroller 3 3V HPS_I2C2_SDAT PIN_A25 I2C Data of the second HPS I2C concontroller 3 3V 3 6 7 VGA Output The DE10 Standard board has a 15 pin D SUB connector populated for VGA output The VGA synchronization signals are generated directly from the Cyclone V SoC FPGA and the Analog Devices ADV7123 triple 10 bit high speed video DAC...

Page 37: ...uring the data display interval the RGB data drives each pixel in turn across the row being displayed Finally there is a time period called the front porch d where the RGB signals must again be off before the next hsync pulse can occur The timing of vertical synchronization vsync is similar to the one shown in Figure 3 23 except that a vsync pulse signifies the end of one frame and the start of th...

Page 38: ...2 7 14 2 0 6 56 XGA 60Hz 1024x768 2 1 2 5 15 8 0 4 65 XGA 70Hz 1024x768 1 8 1 9 13 7 0 3 75 XGA 85Hz 1024x768 1 0 2 2 10 8 0 5 95 1280x1024 60Hz 1280x1024 1 0 2 3 11 9 0 4 108 Table 3 17 VGA Vertical Timing Specification VGA mode Vertical Timing Spec Configuration Resolution HxV a lines b lines c lines d lines Pixel clock MHz VGA 60Hz 640x480 2 33 480 10 25 VGA 85Hz 640x480 3 25 480 1 36 SVGA 60Hz...

Page 39: ...Blue 3 3 3V VGA_B 4 PIN_AH19 VGA Blue 4 3 3V VGA_B 5 PIN_AJ17 VGA Blue 5 3 3V VGA_B 6 PIN_AJ16 VGA Blue 6 3 3V VGA_B 7 PIN_AK16 VGA Blue 7 3 3V VGA_CLK PIN_AK21 VGA Clock 3 3V VGA_BLANK_N PIN_AK22 VGA BLANK 3 3V VGA_HS PIN_AK19 VGA H_SYNC 3 3V VGA_VS PIN_AK18 VGA V_SYNC 3 3V VGA_SYNC_N PIN_AJ22 VGA SYNC 3 3V 3 6 8 TV Decoder The DE10 Standard board is equipped with an Analog Device ADV7180 TV deco...

Page 40: ... I O Standard TD_DATA 0 PIN_AG27 TV Decoder Data 0 3 3V TD_DATA 1 PIN_AF28 TV Decoder Data 1 3 3V TD_DATA 2 PIN_AE28 TV Decoder Data 2 3 3V TD_DATA 3 PIN_AE27 TV Decoder Data 3 3 3V TD_DATA 4 PIN_AE26 TV Decoder Data 4 3 3V TD_DATA 5 PIN_AD27 TV Decoder Data 5 3 3V TD_DATA 6 PIN_AD26 TV Decoder Data 6 3 3V TD_DATA 7 PIN_AD25 TV Decoder Data 7 3 3V TD_HS PIN_AH28 TV Decoder H_SYNC 3 3V TD_VS PIN_AG...

Page 41: ...GA Table 3 shows the pin assignment of IR receiver to the FPGA Figure 3 25 Connection between the FPGA and IR Receiver Table 3 21 Pin Assignment of IR Receiver Signal Name FPGA Pin No Description I O Standard IRDA_RXD PIN_W20 IR Receiver 3 3V 3 6 10 IR Emitter LED The board has an IR emitter LED for IR communication which is widely used for operating television device wirelessly from a short line ...

Page 42: ...ription I O Standard IRDA_TXD PIN_W21 IR Emitter 3 3V 3 6 11 SDRAM Memory The board features 64MB of SDRAM with a single 64MB 32Mx16 SDRAM chip The chip consists of 16 bit data line control line and address line connected to the FPGA This chip uses the 3 3V LVCMOS signaling standard Connections between the FPGA and SDRAM are shown in Figure 3 27 and the pin assignment is listed in Table 3 19 ...

Page 43: ... Address 6 3 3V DRAM_ADDR 7 PIN_AF15 SDRAM Address 7 3 3V DRAM_ADDR 8 PIN_AH15 SDRAM Address 8 3 3V DRAM_ADDR 9 PIN_AG13 SDRAM Address 9 3 3V DRAM_ADDR 10 PIN_AG12 SDRAM Address 10 3 3V DRAM_ADDR 11 PIN_AH13 SDRAM Address 11 3 3V DRAM_ADDR 12 PIN_AJ14 SDRAM Address 12 3 3V DRAM_DQ 0 PIN_AK6 SDRAM Data 0 3 3V DRAM_DQ 1 PIN_AJ7 SDRAM Data 1 3 3V DRAM_DQ 2 PIN_AK7 SDRAM Data 2 3 3V DRAM_DQ 3 PIN_AK8 ...

Page 44: ..._AK13 SDRAM Clock Enable 3 3V DRAM_CLK PIN_AH12 SDRAM Clock 3 3V DRAM_WE_N PIN_AA13 SDRAM Write Enable 3 3V DRAM_CS_N PIN_AG11 SDRAM Chip Select 3 3V 3 6 12 PS 2 Serial Port The DE10 Standard board comes with a standard PS 2 interface and a connector for a PS 2 keyboard or mouse Figure 3 28 shows the connection of PS 2 circuit to the FPGA Users can use the PS 2 keyboard and mouse on the DE10 Stand...

Page 45: ...in Assignment of PS 2 Signal Name FPGA Pin No Description I O Standard PS2_CLK PIN_AB25 PS 2 Clock 3 3V PS2_DAT PIN_AA25 PS 2 Data 3 3V PS2_CLK2 PIN_AC25 PS 2 Clock reserved for second PS 2 device 3 3V PS2_DAT2 PIN_AB26 PS 2 Data reserved for second PS 2 device 3 3V 3 6 13 A D Converter and 2x5 Header The DE10 Standard has an analog to digital converter LTC2308 which features low noise ...

Page 46: ...pt eight input signals at inputs ADC_IN0 through ADC_IN7 These eight input signals are connected to a 2x5 header as shown in Figure 3 29 More information about the A D converter chip is available in its datasheet It can be found on manufacturer s website or in the directory datasheet of DE10 Standard system CD Figure 3 29 Signals of the 2x5 Header Figure 3 30 shows the connections between the FPGA...

Page 47: ...s and other interfaces connected exclusively Users can control these interfaces to monitor the status of HPS Table 3 22 gives the pin assignment of all the LEDs switches and push buttons Table 3 22 Pin Assignment of LEDs Switches and Push buttons Signal Name HPS GPIO Register bit Function HPS_KEY GPIO54 GPIO1 25 I O HPS_LED GPIO53 GPIO1 24 I O 3 3 7 7 2 2 G Gi ig ga ab bi it t E Et th he er rn ne ...

Page 48: ...X_DATA 2 PIN_B18 GMII and MII receive data 2 3 3V HPS_ENET_RX_DATA 3 PIN_D21 GMII and MII receive data 3 3 3V HPS_ENET_RX_CLK PIN_G20 GMII and MII receive clock 3 3V HPS_ENET_RESET_N PIN_E18 Hardware Reset Signal 3 3V HPS_ENET_MDIO PIN_E21 Management Data 3 3V HPS_ENET_MDC PIN_B21 Management Data Clock Reference 3 3V HPS_ENET_INT_N PIN_C19 Interrupt Open Drain Output 3 3V HPS_ENET_GTX_CLK PIN_H19 ...

Page 49: ...ysical interface is implemented by UART USB onboard bridge from a FT232R chip to the host with an USB Mini B connector More information about the chip is available on the manufacturer s website or in the directory Datasheets UART TO USB of DE10 Standard system CD Figure 3 32 shows the connections between the HPS FT232R chip and the USB Mini B connector Table 3 25 lists the pin assignment of UART i...

Page 50: ...s I HPS_DDR3_A 10 PIN_D29 HPS DDR3 Address 10 SSTL 15 Class I HPS_DDR3_A 11 PIN_C30 HPS DDR3 Address 11 SSTL 15 Class I HPS_DDR3_A 12 PIN_B30 HPS DDR3 Address 12 SSTL 15 Class I HPS_DDR3_A 13 PIN_C29 HPS DDR3 Address 13 SSTL 15 Class I HPS_DDR3_A 14 PIN_H25 HPS DDR3 Address 14 SSTL 15 Class I HPS_DDR3_BA 0 PIN_E29 HPS DDR3 Bank Address 0 SSTL 15 Class I HPS_DDR3_BA 1 PIN_J24 HPS DDR3 Bank Address ...

Page 51: ... PIN_P25 HPS DDR3 Data 25 SSTL 15 Class I HPS_DDR3_DQ 26 PIN_T29 HPS DDR3 Data 26 SSTL 15 Class I HPS_DDR3_DQ 27 PIN_T28 HPS DDR3 Data 27 SSTL 15 Class I HPS_DDR3_DQ 28 PIN_R27 HPS DDR3 Data 28 SSTL 15 Class I HPS_DDR3_DQ 29 PIN_R26 HPS DDR3 Data 29 SSTL 15 Class I HPS_DDR3_DQ 30 PIN_V30 HPS DDR3 Data 30 SSTL 15 Class I HPS_DDR3_DQ 31 PIN_W29 HPS DDR3 Data 31 SSTL 15 Class I HPS_DDR3_DQS_n 0 PIN_M...

Page 52: ...able 3 31 Pin Assignment of Micro SD Card Socket Signal Name FPGA Pin No Description I O Standard HPS_SD_CLK PIN_A16 HPS SD Clock 3 3V HPS_SD_CMD PIN_F18 HPS SD Command Line 3 3V HPS_SD_DATA 0 PIN_G18 HPS SD Data 0 3 3V HPS_SD_DATA 1 PIN_C17 HPS SD Data 1 3 3V HPS_SD_DATA 2 PIN_D17 HPS SD Data 2 3 3V HPS_SD_DATA 3 PIN_B16 HPS SD Data 3 3 3V 3 3 7 7 6 6 2 2 p po or rt t U US SB B H Ho os st t The b...

Page 53: ...D15 HPS USB_DATA 6 3 3V HPS_USB_DATA 7 PIN_M17 HPS USB_DATA 7 3 3V HPS_USB_DIR PIN_E14 Direction of the Data Bus 3 3V HPS_USB_NXT PIN_A14 Throttle the Data 3 3V HPS_USB_RESET PIN_G17 HPS USB PHY Reset 3 3V HPS_USB_STP PIN_C15 Stop Data Stream on the Bus 3 3V 3 3 7 7 7 7 A Ac cc ce el le er ro om me et te er r G G s se en ns so or r The board comes with a digital accelerometer sensor module ADXL345...

Page 54: ...T PIN_C24 HPS I2C Data share bus 3 3V 3 3 7 7 8 8 L LT TC C C Co on nn ne ec ct to or r The board has a 14 pin header which is originally used to communicate with various daughter cards from Linear Technology It is connected to the SPI Master and I2C ports of HPS The communication with these two protocols is bi directional The 14 pin header can also be used for GPIO SPI or I2C based communication ...

Page 55: ..._E24 SPI Master Input Slave Output 3 3V HPS_SPIM_MOSI PIN_D22 SPI Master Output Slave Input 3 3V HPS_SPIM_SS PIN_D24 SPI Slave Select 3 3V 3 3 7 7 9 9 1 12 28 8x x6 64 4 D Do ot ts s L LC CD D The board equips an LCD Module with 128x64 dots for display capabilities The LCD module uses serial peripheral interface to connect with the HPS To use the LCD module please refer to the datasheet folder in ...

Page 56: ...ble 3 28 LCD Module Pin Assignments Signal Name FPGA Pin No Description I O Standard HPS_LCM_D_C PIN_C18 HPS LCM Data bit is Data Command 3 3V HPS_LCM_RST_N PIN_E17 HPS LCM Reset 3 3V HPS_LCM_SPIM_CLK PIN_A23 SPI Clock 3 3V HPS_LCM_SPIM_MOSI PIN_C22 SPI Master Output Slave Input 3 3V HPS_LCM_SPIM_SS PIN_H20 SPI Slave Select 3 3V ...

Page 57: ... sdc Pin assignment document htm The above files generated by the DE10 Standard System Builder can also prevent occurrence of situations that are prone to compilation error when users manually edit the top level design file or place pin assignment The common mistakes that users encounter are Board is damaged due to incorrect bank voltage setting or pin assignment Board is malfunctioned because of ...

Page 58: ... design logic The Quartus II setting file contains information such as FPGA device type top level pin assignment and the I O standard for each user defined I O pin Finally the Quartus II programmer is used to download sof file to the development board via JTAG interface Figure 4 1 Design flow of building a project from the beginning to the end 4 4 3 3 U Us si in ng g D DE E1 10 0 S St ta an nd da ...

Page 59: ...r to a host computer without installing the utility A window will pop up as shown in Figure 4 2 after executing the DE10 Standard SystemBuilder exe on the host computer Figure 4 2 The GUI of DE10 Standard System Builder Enter Project Name Enter the project name in the circled area as shown in Figure 4 3 The project name typed in will be assigned automatically as the name of your top level design e...

Page 60: ...figuration to include their choice of components in the project as shown in Figure 4 4 Each component onboard is listed and users can enable or disable one or more components at will If a component is enabled the DE10 Standard System Builder will automatically generate its associated pin assignment including the pin name pin location pin direction and I O standard ...

Page 61: ...rasic GPIO based or HSMC based daughter cards to the GPIO connector or HSMC connector on DE10 Standard the DE10 Standard System Builder can generate a project that include the corresponding module as shown in Figure 4 5 It will also generate the associated pin assignment automatically including pin name pin location pin direction and I O standard ...

Page 62: ...x Name is an optional feature that denote the pin name of the daughter card assigned in your design Users may leave this field blank Project Setting Management The DE10 Standard System Builder also provides the option to load a setting or save users current board configuration in cfg file as shown in Figure 4 6 ...

Page 63: ... 1 Table 4 1 Files generated by the DE10 Standard System Builder No Filename Description 1 Project name v Top level Verilog HDL file for Quartus II 2 Project name qpf Quartus II Project File 3 Project name qsf Quartus II Setting File 4 Project name sdc Synopsis Design Constraints file for Quartus II 5 Project name htm Pin Assignment Document Users can add custom logic into the project in Quartus I...

Page 64: ...d d F Fa ac ct to or ry y C Co on nf fi ig gu ur ra at ti io on n The DE10 Standard board has a default configuration bit stream pre programmed which demonstrates some of the basic features onboard The setup required for this demonstration and the location of its files are shown below Demonstration Setup File Locations and Instructions Project directory DE10_Standard_Default Bitstream used DE10_St...

Page 65: ...program the FPGA and EPCS device 5 5 2 2 A Au ud di io o R Re ec co or rd di in ng g a an nd d P Pl la ay yi in ng g This demonstration shows how to implement an audio recorder and player on DE10 Standard board with the built in audio CODEC chip It is developed based on Qsys and Eclipse Figure 5 2 shows the buttons and slide switches used to interact this demonstration onboard Users can configure ...

Page 66: ... The I2C pins from the audio chip are connected to Qsys system interconnect fabric through PIO controllers The audio chip is configured in master mode in this demonstration The audio interface is configured as 16 bit I2S mode 18 432MHz clock generated by the PLL is connected to the MCLK XTI pin of the audio chip through the audio controller Figure 5 3 Block diagram of the audio recorder and player...

Page 67: ...process will stop if the audio data is played completely 5 5 3 3 K Ka ar ra ao ok ke e M Ma ac ch hi in ne e This demonstration uses the microphone in line in and line out ports on DE10 Standard to create a Karaoke machine The WM8731 CODEC is configured in master mode The audio CODEC generates AD DA serial bit clock BCK and the left right channel clock LRCK automatically The I2C interface is used ...

Page 68: ...olor Connect the audio output of a music player such as a MP3 player or computer to the line in port blue color Connect a headset speaker to the line out port green color Load the bitstream into the FPGA by executing the batch file test bat in the directory DE10_Standard _i2sound demo_batch Users should be able to hear a mixture of microphone sound and the sound from the music player Press KEY0 to...

Page 69: ...er IP accesses SDRAM and how the Nios II processor reads and writes the SDRAM for hardware verification The SDRAM controller handles complex aspects of accessing SDRAM such as initializing the memory device managing SDRAM banks and keeping the devices refreshed at certain interval System Block Diagram Figure 5 6 shows the system block diagram of this demonstration The system requires a 50 MHz cloc...

Page 70: ...ache_flush_all to make sure all the data are written to the SDRAM It then reads data from the SDRAM for data verification The program will show the progress in nios terminal when writing reading data to from the SDRAM When the verification process reaches 100 the result will be displayed in nios terminal Design Tools Quartus II v16 1 Nios II Eclipse v16 1 Demonstration Source Code Quartus project ...

Page 71: ... Demonstration Setup Quartus II v16 1 and Nios II v16 1 must be pre installed on the host PC Power on the DE10_Standard board Connect the DE10_Standard board J13 to the host PC with a USB cable and install the USB Blaster II driver if necessary Execute the demo batch file test bat from the directory SDRAM_Nios_Test demo_batch After the program is downloaded and executed successfully a prompt messa...

Page 72: ...RAM test with its test code written in Verilog HDL The memory size of the SDRAM bank tested is still 64MB Function Block Diagram Figure 5 8 shows the function block diagram of this demonstration The SDRAM controller uses 50 MHz as a reference clock and generates 100 MHz as the memory clock Figure 5 8 Block diagram of the SDRAM test in Verilog RW_test module writes the entire memory with a test seq...

Page 73: ...PC Connect the DE10_Standard board J13 to the host PC with a USB cable and install the USB Blaster II driver if necessary Power on the DE1_SoC board Execute the demo batch file DE10_Standard _SDRAM_RTL_Test bat from the directoy DE10_Standard _SDRAM_RTL_Test demo_batch Press KEY0 on the DE1_SoC board to start the verification process When KEY0 is pressed the LEDR 2 0 should turn on When KEY0 is th...

Page 74: ...me period upon power up and the Lock Detector block is responsible for detecting this instability The ITU R 656 Decoder block extracts YcrCb 4 2 2 YUV 4 2 2 video signals from the ITU R 656 data stream sent from the TV decoder It also generates a data valid control signal which indicates the valid period of data output De interlacing needs to be performed on the data source because the video signa...

Page 75: ...ile DE10_Standard _TV sof D De em mo on ns st tr ra at ti io on n S Se et tu up p F Fi il le e L Lo oc ca at ti io on ns s a an nd d I In ns st tr ru uc ct ti io on ns s Connect a DVD player s composite video output yellow plug to the Video in RCA jack J6 on the DE10_Standard board as shown in Figure 5 10 The DVD player has to be configured to provide NTSC output 60Hz refresh rate 4 3 aspect ratio...

Page 76: ...m mo on ns st tr ra at ti io on n A simply PS 2 controller coded in Verilog HDL is provided to demonstrate bi directional communication with a PS 2 mouse A comprehensive PS 2 controller can be developed based on it and more sophisticated functions can be implemented such as setting the sampling rate or resolution which needs to transfer two data bytes at once More information about the PS 2 protoc...

Page 77: ...rocess or to indicate the start of a new transmission process which is usually called as inhibit state It then pulls low the data line before releasing the clock line This is called the request state The rising edge on the clock line formed by the release action can also be used to indicate the sample time point as for a start bit The device will detect this succession and generates a clock sequen...

Page 78: ...0_Standard _PS2 Bitstream used DE10_Standard _PS2 sof D De em mo on ns st tr ra at ti io on n B Ba at tc ch h F Fi il le e Demo batch file directoy DE10_Standard _PS2 demo_batch The folder includes the following files Batch file test bat FPGA configuration file DE10_Standard _PS2 sof D De em mo on ns st tr ra at ti io on n S Se et tu up p F Fi il le e L Lo oc ca at ti io on ns s a an nd d I In ns ...

Page 79: ...cator LEDR 2 Middle button press indicator HEX0 Low byte of X displacement HEX1 High byte of X displacement HEX2 Low byte of Y displacement HEX3 High byte of Y displacement 5 5 8 8 I IR R E Em mi it tt te er r L LE ED D a an nd d R Re ec ce ei iv ve er r D De em mo on ns st tr ra at ti io on n DE10_Standard system CD has an example of using the IR Emitter LED and IR receiver This demonstration is ...

Page 80: ... be 50MHz The NEC IR transmission protocol uses pulse distance to encode the message bits Each pulse burst is 562 5µs in length with a carrier frequency of 38kHz 26 3µs Figure 5 13 shows the duration of logical 1 and 0 Logical bits are transmitted as follows Logical 0 a 562 5µs pulse burst followed by a 562 5µs space with a total transmit time of 1 125ms Logical 1 a 562 5µs pulse burst followed by...

Page 81: ...eceive a 9 ms low and then 4 5 ms high lead code IR Remote When a key on the remote control shown in Figure 5 15 is pressed the remote control will emit a standard frame as shown in Table 5 5 The beginning of the frame is the lead code which represents the start bit followed by the key related information The last bit end code represents the end of the frame The value of this frame is completely i...

Page 82: ...ontroller in the FPGA Figure 5 17 shows the modules used in this demo including Code Detector State Machine and Shift Register At the beginning the IR receiver demodulates the signal inputs to the Code Detector The Code Detector will check the Lead Code and feedback the examination result to the State Machine The State Machine block will change the state from IDLE to GUIDANCE once the Lead Code is...

Page 83: ...roject directory DE10_Standard_IR Bitstream used DE10_Standard_IR sof D De em mo on ns st tr ra at ti io on n B Ba at tc ch h F Fi il le e Demo batch file directory DE10_Standard_IR demo_batch The folder includes the following files Batch file test bat FPGA configuration file DE10_Standard_IR sof D De em mo on ns st tr ra at ti io on n S Se et tu up p F Fi il le e L Lo oc ca at ti io on ns s a an ...

Page 84: ...on HEX5 Inversed high byte of DATA Key Code HEX4 Inversed low byte of DATA Key Code HEX3 High byte of ADDRESS Custom Code HEX2 Low byte of ADDRESS Custom Code HEX1 High byte of DATA Key Code HEX0 Low byte of DATA Key Code 5 5 9 9 A AD DC C R Re ea ad di in ng g This demonstration illustrates steps to evaluate the performance of the 8 channel 12 bit A D Converter LTC2308 The DC 5 0V on the 2x5 head...

Page 85: ...ter in the convertor via serial interface and translates it to voltage value to be displayed on the Nios II console Figure 5 20 Pin distribution of the 2x5 Header for the ADC The LTC2308 is a low noise 500ksps 8 channel 12 bit ADC with an SPI MICROWIRE compatible serial interface The internal conversion clock allows the external serial output data clock SCK to operate at any frequency up to 40MHz ...

Page 86: ...en SCK is set to 40MHz it means 25ns per unit The default tHCONVST is set to 320 achieving a 100KHz fsample Thus adding more tHCONVST time by increasing tHCONVST macro value will lower the sample rate of the ADC Converter define tHCONVST 320 Figure 5 22 shows the example MUX configurations of ADC In this demonstration it is configured as 8 signal end channel in the verilog code User can change SW ...

Page 87: ... Trimmer Potentiometer x1 Wire Strip x3 Demonstration File Locations Hardware project directory DE10_Standard _ADC Bitstream used DE10_Standard _ADC sof Software project directory DE10_Standard _ADC software Demo batch file DE10_Standard _ADC demo_batch DE10_Standard _ADC bat Demonstration Setup and Instructions Connect the trimmer to corresponding ADC channel on the 2x5 header as shown in Figure ...

Page 88: ...ile DE10_Standard _ADC bat to load the bitstream and software execution file to the FPGA The Nios II console will display the voltage of the specified channel voltage result information Provide any input voltage to other ADC channels and set SW 2 0 to the corresponding channel if user want to measure other channels Figure 5 23 Hardware setup for the ADC reading demonstration ...

Page 89: ...o run Linux on DE10_Standard board Installation of the Demonstrations To install the demonstrations on the host computer Copy the directory Demonstrations into a local directory of your choice Intel SoC EDS v16 1 is required for users to compile the c code project 6 6 1 1 H He el ll lo o P Pr ro og gr ra am m This demonstration shows how to develop first HPS program with Altera SoC EDS tool Please...

Page 90: ...e a project by executing C intelFPGA 16 1 embedded Embedded_Command_Shell bat The cd command can change the current directory to where the Hello World project is located The make command will build the project The executable file my_first_hps will be generated after the compiling process is successful The clean all command removes all temporary files Demonstration Source Code Build tool SoC EDS v1...

Page 91: ... Altera Yocto Linux Type my_first_hps in the UART terminal of PuTTY to start the program and the Hello World message will be displayed in the terminal 6 6 2 2 U Us se er rs s L LE ED D a an nd d K KE EY Y This demonstration shows how to control the users LED and KEY by accessing the register of GPIO controller through the memory mapped device driver The memory mapped device driver allows developer...

Page 92: ... modules Figure 6 2 shows the block diagram of GPIO Interface GPIO 28 0 is controlled by the GPIO0 controller and GPIO 57 29 is controlled by the GPIO1 controller GPIO 70 58 and input only GPI 13 0 are controlled by the GPIO2 controller Figure 6 2 Block diagram of GPIO Interface GPIO Register Block The behavior of I O pin is controlled by the registers in the register block There are three 32 bit ...

Page 93: ...r controls the output value of first I O pin in the associated GPIO controller and the second bit controls the output value of second I O pin in the associated GPIO controller and so on The value 1 in the register bit indicates the output value is high and the value 0 indicates the output value is low The status of KEY can be queried by reading the value of gpio_ext_porta register The first bit re...

Page 94: ...t_write_word write a value into a specified register munmap clean up memory mapping close close device driver Developers can also use the following MACRO to access the register alt_setbits_word set specified bit value to one for a specified register alt_clrbits_word set specified bit value to zero for a specified register The program must include the following header files to use the above API to ...

Page 95: ...ction of HPS_GPIO29 The bit 24 controls the pin direction of HPS_GPIO53 which connects to HPS_LED the bit 25 controls the pin direction of HPS_GPIO54 which connects to HPS_KEY and so on The pin direction of HPS_LED and HPS_KEY are controlled by the bit 24 and bit 25 in the gpio_swporta_ddr register of the GPIO1 controller respectively Similarly the output status of HPS_LED is controlled by the bit...

Page 96: ...io_ext_porta register The bit mask is used to check the status of the key alt_read_word virtual_base uint32_t ALT_GPIO1_EXT_PORTA_ADDR uint32_t HW_REGS_MASK Demonstration Source Code Build tool SoC EDS V16 1 Project directory Demonstration SoC hps_gpio Binary file hps_gpio Build command make make clean to remove all temporal files Execute command hps_gpio Demonstration Setup Connect a USB cable to...

Page 97: ...uilt in I2C kernel driver in Altera Soc Yocto Powered Embedded Linux Function Block Diagram Figure 6 6 shows the function block diagram of this demonstration The G sensor on the DE1_SoC board is connected to the I2C0 controller in HPS The G Sensor I2C 7 bit device address is 0x53 The system I2C bus driver is used to access the register files in the G sensor The G sensor interrupt signal is connect...

Page 98: ...ata8 sizeof unsigned char The step 4 above can also be changed to the following to read multiple byte values read file szData8 sizeof szData8 where szData is an array of bytes The step 4 above can be changed to the following to write multiple byte values write file szData8 sizeof szData8 where szData is an array of bytes G sensor Control The ADI ADXL345 provides I2C and SPI interfaces I2C interfac...

Page 99: ...l files Execute command gsensor loop count Demonstration Setup Connect a USB cable to the USB to UART connector J4 on the DE10_Standard board and the host PC Copy the executable file gsensor into the microSD card under the home root folder in Linux Insert the booting microSD card into the DE10_Standard board Power on the DE10_Standard board Launch PuTTY to establish connection to the UART port of ...

Page 100: ...onnected to HPS_GPIO48 which is bit 19 of the GPIO1 controller Once HPS gets access to the I2C bus it can then access Audio CODEC and TV Decoder when the HPS_I2C_CONTROL signal is set to high The following mask in the demo code is defined to control the direction and output value of HPS_I2C_CONTROL define HPS_I2C_CONTROL 0x00080000 The following statement is used to configure the HPS_I2C_CONTROL a...

Page 101: ...S v16 1 Project directory Demonstration SoC hps_i2c_switch Binary file i2c_switch Build command make make clean to remove all temporal files Execute command i2c_switch Demonstration Setup Connect a USB cable to the USB to UART connector J4 on the DE10_Standard board and host PC Copy the executable file i2c_switch into the microSD card under the home root folder in Linux Insert the booting microSD ...

Page 102: ... LCD is write only only three SPI signals LCM_SPIM_CLK LCM_SPIM_SS and LCM_SPIM_MOSI are required The LCM_D_C signal is used to indicate the signal transferred on the SPI bus is Data or Command When LCM_D_C signal is pulled high it means the signal on SPI bus is Data When LCM_D_C signal is pulled low it means the signal on SPI bus is Command The LCD_RST_n is the reset control signal of LCD This si...

Page 103: ...th clock rate 3 125MHz Please refer to the function LCDHW_Init in LCD_Hw c for details The header file socal alt_spim h which needs to be included into the SPI controller program defines all necessary constants for the SPIM controller C code Explanation This demonstration includes the following major files LCD_HW c Low level SPI and GPIO API to access LCD hardware LCD_Driver c LCD configuration AP...

Page 104: ... Build tool SoC EDS v16 1 Project directory Demonstration SoC hps_lcd Binary file hps_lcd Build command make make clean to remove all temporary files Execute command hps_lcd Demonstration Setup Connect the USB cable to the USB to UART connector J4 on the DE10 Standard board and host PC Make sure the executable file hps_lcd is copied into the SD card under the home root folder in Linux Insert the b...

Page 105: ...DE10 Standard User Manual 104 www terasic com January 19 2017 Figure 6 14 LCD display for the LCD Demonstration ...

Page 106: ...A is configured by HPS through FPGA manager in HPS 7 7 1 1 R Re eq qu ui ir re ed d B Ba ac ck kg gr ro ou un nd d This section pre assumed the developers have the following background knowledge FPGA RTL Design Basic Quartus II operation skill Basic RTL coding skill Basic Qsys operation skill Knowledge about Memory Mapped Interface C Program Design Basic SoC EDS Embedded Design Suite operation ski...

Page 107: ...alled SoC EDS 16 0 or Later Installed Win32 Disk Imager Installed 7 7 3 3 A AX XI I b br ri id dg ge es s i in n I In nt te el l S So oC C F FP PG GA A In Intel SoC FPGA the HPS logic and FPGA fabric are connected through the AXI Advanced eXtensible Interface bridge For HPS logic to communicate with FPGA fabric Intel system integration tool Qsys should be used for the system design to add HPS comp...

Page 108: ...ss most slaves in the HPS For example the FPGA to HPS bridge can access the accelerator coherency All three bridges contain global programmer view GPV register The GPV register control the behavior of the bridge It is able to access to the GPV registers of all three bridges through the lightweight HPS to FPGA bridge This Demo introduces to users how to use the HPS ARM to communicate with FPGA This...

Page 109: ...stem Console System ID The memory map of system peripherals in the FPGA portion of the SoC as viewed by the MPU starts at the lightweight HPS to FPGA base address 0xFF20_0000 The MPU can access these peripherals through the Address offset setting in the Qsys User can open the GHRD project with Quartus II Software Then open the soc_system qsys file with the Qsys tool Figure 7 2 lists the address ma...

Page 110: ...cess by clicking the menu item Processing Start Compilation Because tcl files of SDRAM DDR3 controller for HPS had been executed in GHRD project developers can skip this procedure If developers Quartus project is not developed based on the GHRD project please remember to execute the tcl files of SDRAM DDR3 controller as show in Figure 7 4 before executing Start Compilation The TCL Scripts dialog c...

Page 111: ...oller SoC EDS is used to compile the C project For ARM program to control the led_pio PIO component led_pio address is required The Linux built in driver dev mem and mmap system call are used to map the physical base address of led_pio component to a virtual address which can be directly accessed by Linux application software HPS Header File pio_led component information is required for ARM C prog...

Page 112: ...address into a virtual address which is accessible by an application software Figure 7 6 shows the C program to derive the virtual address of led_pio base address First open system call is used to open memory device driver dev mem and then the mmap system call is used to map HPS physical address into a virtual address represented by the void pointer variable virtual_base Then the virtual address o...

Page 113: ...IO Core Each register is 32 bit width For detail information please refer to the datasheet of PIO Core For led control we just need to write output value to the offset 0 register relative to based address 0x10040 Because the led on DE10 Standard is high active writing a value 0x00000000 to the offset 0 register will turn off all of the nine red LEDs There are 10 red LEDs on DE10 Standard and 9 of ...

Page 114: ...orm LED light sifting operation as shown in Figure 7 8 When finishing 60 times of shift cycle the program will be terminated Figure 7 8 Program for LED Shift Operation Makefile and compile Figure 7 9 shows the content of Makefile for this C project The program includes the head files provided by SoC EDS In the Makefile ARM linux cross compile also be specified ...

Page 115: ...tion file HPS_FPGA_LED Figure 7 10 ARM C Project Compilation Execute the Demo To execute the demo please boot the Linux from the SD card in DE10 Standard Copy the execution file HPS_FPGA_LED to the Linux directory and type chmod x HPS_FPGA_LED to add execution attribute to the execute file Use Quartus Programmer to configure FPGA with the DE10_NANO_SoC_GHRD sof generated in previous chapter ...

Page 116: ...he ARM program The LED 9 1 on DE10 Standard I will be expected to perform 60 times of LED light shift operation and then the program is terminated For details about booting the Linux from SD card please refer to the document Getting_Started_Guide pdf For details about copying files to Linux directory please refer to the document My_First_HPS pdf ...

Page 117: ...ser specified SRAM object file sof in Quartus The sof file is generated after the project compilation is successful The steps of converting sof to jic in Quartus II are listed below 8 8 1 1 B Be ef fo or re e P Pr ro og gr ra am mm mi in ng g B Be eg gi in ns s The FPGA should be set to AS x1 mode i e MSEL 4 0 10010 to use the quad Flash as a FPGA configuration device 8 8 2 2 C Co on nv ve er rt t...

Page 118: ...he Programming file type field in the dialog of Convert Programming Files 3 Choose EPCS128 from the Configuration device field 4 Choose Active Serial from the Mode filed 5 Browse to the target directory from the File name field and specify the name of output file 6 Click on the SOF data in the section of Input files to convert as shown in Figure 8 2 ...

Page 119: ...e 8 2 Dialog of Convert Programming Files 7 Click Add File 8 Select the sof to be converted to a jic file from the Open File dialog 9 Click Open 10 Click on the Flash Loader and click Add Device as shown in Figure 8 3 11 Click OK and the Select Devices page will appear ...

Page 120: ... com January 19 2017 Figure 8 3 Click on the Flash Loader 12 Select the targeted FPGA to be programed into the EPCS as shown in Figure 8 4 13 Click OK and the Convert Programming Files page will appear as shown in Figure 8 5 14 Click Generate ...

Page 121: ...DE10 Standard User Manual 120 www terasic com January 19 2017 Figure 8 4 Select Devices page ...

Page 122: ...te please follow the steps below to program the EPCS device with the jic file created in Quartus II Programmer 1 Set MSEL 4 0 10010 2 Choose Programmer from the Tools menu and the Chain cdf window will appear 3 Click Auto Detect and then select the correct device Both FPGA device and HPS should be detected as shown in Figure 8 6 4 Double click the green rectangle region shown in Figure 8 6 and the...

Page 123: ...9 2017 5 Program the EPCS device by clicking the corresponding Program Configure box A factory default SFL image will be loaded as shown in Figure 8 7 6 Click Start to program the EPCS device Figure 8 6 Two devices are detected in the Quartus II Programmer ...

Page 124: ...ice are 1 Set MSEL 4 0 10010 2 Choose Programmer from the Tools menu and the Chain cdf window will appear 3 Click Auto Detect and then select correct device both FPGA device and HPS will detected See Figure 8 6 4 Double click the green rectangle region shown in Figure 8 6 and the Select New Programming File page will appear Select the correct jic file 5 Erase the EPCS device by clicking the corres...

Page 125: ...DE10 Standard User Manual 124 www terasic com January 19 2017 image will be loaded as shown in Figure 8 8 Figure 8 8 Erase the EPCS device in Quartus II Programmer 6 Click Start to erase the EPCS device ...

Page 126: ...nual 125 www terasic com January 19 2017 Chapter 9 Appendix 9 9 1 1 R Re ev vi is si io on n H Hi is st to or ry y Version Change Log V0 1 Initial Version Preliminary Copyright 2017 Terasic Technologies All rights reserved ...

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