Circuit
Description
—
Type
3B5
For
all
sweep
rates,
the
VARIABLE
control,
R397,
adds
additional
resistance
in
series
with
the
Timing
Resistor
when
not
in
the
CAL
detent.
This
provides
continuously
variable,
uncalibrated
sweep
rates
between
the 1-2-5
steps.
Also
note
that
this
control is
ganged
with
SW397
to
turn
on
the
UNCAL
readout
and
turn off
the
s/DIV
readout
(see
s/DIV
and
UNCAL Readout Control).
s/DIV
and
UNCAL
Readout
Control
SW397
is ganged
with
the VARIABLE
control,
R397.
When
the
VARIABLE
control
is
in
the
CAL
detent, B999,
s/DIV
readout,
is
connected into
the circuit. However, whenever
the
VARIABLE
control is turned
away
from
the
CAL
detent,
SW397
turns
off
B999
and
turns
on
B987,
UNCAL
readout,
to
indicate
that
the
sweep
rate is
not
calibrated.
The
current
through
B987 or
B999
from
the
—12.2
volts
supply
provides
current
to
the
—
6
volt
line
for
the
heater
of
V1
63.
This
current
is
provided
in
parallel
with
current
supplied
by
the
mode-indicating
bulbs in
the Operating
Mode
Power
circuit.
X10
and X100
Magnifier
Gates
Q364
is
the
X10
Magnifier
Gate
and
Q324
is
the XI
00
Magnifier
Gate.
When
both of
these
transistors
are
on,
the
sweep
magnification
is
X
1. X10
delayed
sweep
magnifi
cation
is provided when Q364
is
off
and
Q324
remains
on.
When
both
Q364
and
Q324
are
off,
the
delayed
sweep
magnification
is X1
00.
R381,
R384
and
R387
are
the X1
timing
resistors.
Only
one of
these
resistors
supplies
timing
current
for X
1
sweep
magnification
as
selected
by
the
multiplier
logic.
For
example,
Fig.
3-14
shows
the timing-current
path for
a
sweep
rate
of
one
millisecond/division
with
X1
sweep
magnifica
tion.
The
1 ms
(d)
decade
logic
actuates
K310
and
K313
to
select
the
1
ms
decade.
D392
and
D393
are
forward
biased
by
the
multiplier
logic
(approximately
zero
volts)
applied
to
the
"2
”
and
“
5”
logic
lines
and
the
"2
”
and
‘‘5
”
timing
currents
are
shunted.
—
12
volts
on
the
"1"
logic
line reverse
biases
D391
and
allows
the
"T"
timing current
to
pass
to
the
Timing
Capacitor
through
D317.
The
X10
Magnifier
Gate
is
held
on
by
the
XI
magnifier
logic
applied
to
the
Delay
Comparator
(see
Delay
Comparator
discussion).
This
places
the
collector
of Q364 near
zero
volts
and
the
X10
timing
current is
shunted
through
D367,
D366
and
Q
364.
The
X
1
00
Magnifier
Gate is
held
on
by
the
X
1
00
(bar
X
1
00
magnifier)
logic.
The
X
1
00
timing current
is
shunted
through
D327
and
Q324. Therefore,
only
the
timing
current
through
R381
charges
the
Timing
Capacitor.
For
X10
delayed
sweep
magnification,
X10
timing
cur
rent
through
R382,
R385
or
R388
is
added
to
the
X1
timing
current.
The
Delay
Comparator
switches
Q364
off
at
the
sweep level
selected
by
the
DELAY
control
(note
exception
for
0.1
μ
s
and
10
ns
decades;
see
Delay
Comparator
discus
sion).
When
the comparator
switches,
the
collector
of
Q356
goes
positive.
This
decreases
the
current
through
tunnel
diode
D365
and
it
switches from its high-voltage
state
to
its low-voltage
state.
D365
produces
a
fast
voltage
change
at
the
base
of
Q364
to
turn
it
off
quickly.
When
Q364
turns
off,
its
collector
drops
to
about
—
12
volts
and
the
X10
shunt diodes
D367-D368-D369
are reverse
biased.
X10
timing
current
is
added to
the
XI
timing
current
in
the
timing
group
that
is
charging
the Timing
Capacitor
(as
determined
by
the
multiplier
logic).
The
timing
current
in
the
other
two
timing
groups
is
shunted
away
from
the
timing
capacitor.
For
example,
Fig.
3-15 shows
the
timing
current
path for
X10
delayed
sweep magnification
at
a
magnified
sweep
rate
of
0.1
millisecond/division.
Note
that
the
same
Timing
Capacitor
is used
as
in
the previous
example
for
X
1
magnification. D391
is reverse
biased
by
the
multiplier
logic
applied
to
the
"1
"-logic
line
to allow
timing
current
to
charge
the
Timing
Capacitor
through
D317.
The
total
X10
timing
current
is
supplied through
both R381
and
R382.
This
total
timing
current
is
10
times
greater
than
the
X1
timing
current
to
increase
the
sweep
rate
10
times.
The
X100
timi
ng
cur
rent
is
shunted
by
D327
since
Q364
is
held
on
by
the
X
1
00
magnifier
logic
level.
For
X
100
delayed
sweep
magnification
the
X10
Mag
nifier
Gate
still
controls
the
starting
point
of
the
magnified
sweep
as
described
for
X10
operation.
The
X
1
00
timing
current is
a combination
of
the
X
1,
X10 and X
100
timing
current.
R383,
R386
and
R389
are
the
X
1
00
timing
resistors.
The
X
1
00
Magnifier
Gate
is
controlled
by
several
logic
levels.
For
the
1
μ
s
timing
decade,
the
1
μ
s (g)
logic
line
is
at
—12
volts.
Since
its
base
is
held
negative,
Q324
is
conducting
and the
X
100
timing
current
is
locked
out
through
D327,
D328
or
D329.
In
the
0.1
μ
s
and
10
ns
timing
decades,
the
0.1
μ
s
(h)
logic
line
is
at
—12
volts
and
the
X
1
00
timing
current
is
similarly
locked
out.
These
logic
levels
prevent
sweep
rates
faster
than
10
microsecond
s/divi-
sion from being magnified 100 times.
In
addition,
the
X
1
00
magnifier
logic
holds
the X
100
Magnifier
Gate
on
for
X
1
and
X10
sweep
magnification.
However,
for X100
sweep
magnification
the
X
1
00
magnifier
logic
is
zero
volts
and
Q324
is
reverse
biased.
The
collector
of Q324
goes
to
about
—12
volts
and
the
X
1
00
shunt diodes,
D327-D328-D329,
are
reverse
biased.
Since
the
X10
Magnifier
Gate still
con
trols
the
turn-on
point
for
the delayed
sweep
magnifier,
the
X
100
timing
current
is
shunted
along
with
the
X10
timing
current.
Then,
as
the
X10
Magnifier
Gate
is turned
on,
both
the
X10
and
X100
timing current are
added
to
the
X
1
timing
current
to charge the
Timing
Capacitor.
This
pro
duces
a
sweep
rate
100
times
faster
than
the
basic X1
sweep
rate.
Fig.
3-16
shows
the
timing
current
path
for
delayed
sweep
magnification
at
a
magnified
sweep
rate
of
10
microseconds/division
with X100
magnification.
The
total
X
1
00
timing
current
is
supplied
through
R381,
R382
and
R383.
This
total current is 100
times
greater
than
the
X
1
timing current
to
increase
the
sweep
rate
100 times.
NOTE
Although
the
DLY’D
SWP MAG
switch
can
be
set
to
X
1
00
for
sweep
rates
of
1,
2
and
5
μ
s, only
X10
delayed
sweep
magnification
is
provided.
Sweep
rates
between
10
ns
and
0.5
μ
s
cannot
be
magnified
with
the
delayed
sweep
magnifier.
Delayed
Sweep
Magnifier
Intensifier
Q374
provides
an
intensifying
pulse to
the
grid
circuit
of
the
indicator
oscilloscope
CRT
to
compensate
for
the
lower
display
intensity
when
the
sweep
is
magnified
_ [due
to
increased
sweep
rate.)
For
X
1
magnification,
the
X1
mag
nifier
logic
level
at
the
anode
of
D371 is zero
volts.
This
clamps
the
base
of
Q374
s
o
it
ca
n
not
go
more
negative
than
about
zero
volts.
The
X
1
00
magnifier
logic level
at
the
anode of
D376
is
—12
volts.
D376
is
reverse
biased
and
3-22
Summary of Contents for 3B5
Page 4: ...Fig 1 1 Type 3B5 Automatic Programmable Time Base unit Type 3B5...
Page 15: ...Operating Instructions Type 3B5 TYPE 3B5 CONTROL SET UP CHART Fig 2 2 Control set up chart 2 7...
Page 48: ...CO I o Fig 3 13 Delay and Timing Circuit logic block diagram Circuit Description Type 3B5...
Page 61: ...GO i GO GO Fig 3 22 Seek Ciicuit Logic block diagram Circuit Description Type 3B5...
Page 70: ...u k KJ Fig 3 29 Circuit conditions for Manual Mode operation Circuit Description Type 3B5...
Page 71: ...w K w Fig 3 30 Circuit conditions for Seek Mode operation Circuit Description Type 3B5...
Page 72: ...w I u U Fig 3 31 Circuit condition for External Mode operation Circuit Description Type 3B5...
Page 88: ...Maintenance Type 3B5 Fig 4 9 Location of components on Logic Card 4 14...
Page 89: ...u Oi Fig 4 10 Location of components on Counter Card Maintenance Type 3B5...
Page 92: ...NOTES I...
Page 104: ...NOTES...
Page 106: ...Calibration Type 3B5 Fig 6 1 Recommended calibration equipment...
Page 160: ......
Page 176: ...J400 RtADOUT BOARD 3B5 PLUG IN A READOUT...
Page 182: ...397 R E A D O U T B O A R D 10 6b READOUT BOARD...
Page 184: ...FIG 1 FRONT SWITCHES TYPE 3B5 AUTOMATIC PROGRAMMABLE TIME BASE...
Page 185: ...FIG 2 CHASSIS REAR 3 GS to TYPE 3B5 AUTOMATIC PROGRAMMABLE TIME BASE...
Page 186: ...OPTIONAL ACCESSORIES...