Tektronix 3B5, Instruction Manual

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Circuit Description —Type 3B5
level follows the base, the voltage at the emitter is about
0.5 volt less positive to establish the desired source voltage.
Bright Baseline
The negative trigger pulses applied to the primary pulses of
T140 are also connected to the Bright Baseline stage through
D281. Q285 and Q295 are connected as a latch circuit with
the collector of Q285 connected to the base of Q295 through
R291 and the collector of Q295 connected to the base of
Q285 through C284-R284-D282. Negative-going trigger pulses
from Q1 34 in the Sweep Trigger circuit are applied to the
base of Q285 to turn it on and its collector goes positive.
This positive-going voltage is connected to the base of Q295
and it also turns on. The collector of Q295 goes negative
to about — 12 volts and C284 begins to charge through R282,
D212, and the base-emitter junction of Q285. This charging
current holds Q285 in conduction and the circuit is latched
up. If only one trigger pulse is applied, the circuit remains
latched up for about 50 milliseconds until C284 is near full
charge and the charging current can no longer hold Q285
in conduction. Then, the latch circuit shuts off and C284
rapidly discharges through D284 and R294. However, if
another trigger pulse (repetitive trigger signal) is applied
to the base of Q285 before C284 is near full charge, Q295
quickly discharges C284 and the recharge cycle begins
again to hold the circuit latched up.
When the latch circuit is on (unit triggered), the base of
Q293 is held negative so current does not flow through
B985, NOT TRIG'D readout. The anode of D299 drops to
about — 6 volts and this level allows the Trigger Latch
Circuit to remain on and the unit operates as set by the
front-panel controls. When the unit is not triggered, the
base of Q293 rises positive to forward bias Q293. The
NOT TRIG'D readout, B985, comes on and the anode of
D299 rises positive enough so it is forward biased. When
D299 conducts it turns the Trigger Latch Circuit off and the
unit switches to auto triggering (Seek Mode only). The
voltage level at the collector of Q44 in the Sweep Trigger
circuit is applied to this stage through D296. This voltage
is about — 12 volts when the instrument is triggered in the
normal trigger mode and it rises to about + 40 volts when
the unit is in the auto trigger mode. For normal triggering,
current flows through D296 or D297 to hold the anode of
D148 negative enough to disconnect the Bright Baseline
stage from the Sweep Gate stage. However, in the auto
trigger mode, D296 is reverse biased and the only current
holding D1 48 reverse biased is through D297 to the Bright
Baseline stage. This current is high enough to hold D1 48
reverse biased when Q293 is off (unit triggered). However,
when Q293 comes on (unit not triggered) the cathode of
D297 rises to about — 5 volts and it is reverse biased. Now,
since D296 is also reverse biased for auto triggering, all
the current through R149 flows through D149 and D148 to
the Sweep Gate tunnel diode. This added current to the
tunnel diode automatically switches it to its high-voltage
state immediately after it is reset. The result is that the
Sweep Generator circuit is automatically retriggered after
the end of each holdoff period and a free-running sweep is
produced. Since this trace free-runs at the sweep rate
produced by the Sweep Generator, it is about the same
intensity at all sweep rates.
Delay and Timing Circuit
General
The Delay and Timing Circuit selects a Timing Resistor
and Timing Capacitor to determine the sweep rate of the
sawtooth produced by the Sweep Generator circuit. The
Timing Capacitor is selected by the decade logic and the
Timing Resistor is selected by the multiplier logic from the
MANUAL TIME/DIV switch or the Counter Circuit. In addi­
tion, the X10 and X 1 00 Magnifier Gates increase the
timing current to provide magnified sweep rates. The Delay
Comparator determines the start of the magnified sweep.
Fig. 3-13 shows a logic block diagram of the Delay and
Timing Circuit. A diagram of this circuit is shown on dia ­
gram 3 at the rear of this manual.
Timing Capacitor
The Timing Capacitor determines the decade range of
the sweep rate. The Timing Capacitor is selected by coils
K310-K315 which actuate corresponding reed relays K310-1 to
K315-1. Decade logic from the Readout Logic Circuit (origi­
nating at the MANUAL TIME/DIV switch or the Counter
Circuit) is applied to the 1 s - 10 μ s decade logic lines (a-f).
To select one of the timing capacitors, the corresponding
decade logic line is dropped to the — 12-volt level. The
remaining logic lines are held at zero volts. For example to
select the 10 μ is decade (10, 20 and 50 μ s sweep rates), —12
volts is applied to
the
10 μ s (f) logic line and current passes
through K315. K315-1 closes to connect C315 and C316
to the Timing Resistor. The 10, 20 or 50 /zs sweep rate within
this decade is selected by the multiplier logic applied to the
Timing Resistor.
To select the 1 ms and slower sweep decades, K310-1 must
be closed in addition to the reed relay which selects the
desired Timing Capacitor. For example, to select the 10 ms
decade, —12 volts is applied to the 10 ms (c) logic line.
Current flows through K312 and K312-1 is actuated. In
addition, D304 is forward biased and current flows through
K310 to actuate K310-1. For the 1 s (a) decade range, an
additional switch is actuated. Current passes through K395
to actuate K.395-1 (located in Timing Resistor stage). R394,
R395 and R398 are connectd into the Timing Resistor circuit
to reduce the timing current through the Timing Resistor 10
times. Since the same Timing Capacitor is used for the 1 s
decade as for the 0.1 s decade, the sweep rate is reduced
10 times. The Timing Capacitor for the 1 μ s and faster
decades is C1 68 (see Sweep Generator discussion). The
X10 Magnifier Gate stage is used to obtain the 0.1 μ s
decade and both the X10 Magnifier Gate stage and a
X10 gain network in the Horizontal Amplifier are used
to obtain the 10 ns decade.
When the decade logic to a coil ends, the collapsing
magnetic field in the coil produces a reverse inductive volt ­
age. A diode is connected across each of the coils to protect
the circuit from this positive-going pulse. D302-D307 pro ­
vide this protection for K310 and K311. Since all logic lines
except one are at zero volts, some of the interconnecting
diodes are forward biased for the positive-going pulse
Delay Comparator
The Delay Comparator stage allows selection of the
amount of delay before the delayed sweep magnifier is
3-19