Tandy 6000 HD, Service Manual

Page: 132 / 416

Service Manual
TANDY 6000/6000-HD
TAN D Y COMPUTER PRODUCTS ----------------------------------------------------------------------
4. TIMING/CONTROL
The TIMING/CONTROL subsection (schematic, sheet 5, 6)
provides the necessary signals to access the memory and
control the data transceiver. This circuity includes the
memory controller U50, RAM timing generator circuit U39,
U 6 2 , U 8 0 , U81 and ROM timing and data transceiver control
U 6 0 , U49. The memory controller U50 decodes the addresses
A11-A15, memory configuration discretes ROM, VIDEO, BANKO,
BANKSEL, LOW PAGE and 16K to determine if a memory access
should be in progress and, if it is, whether it is for ROM
or for RAM. For ROM (ROM = hi, address range 0000-0FFF),
the outputs ROMSEL and ROMAD are true (hi). If for RAM,
BANKO = lo, PAGE = hi (address 0000-FFFF unless VIDEO = hi,
then address 0000-F800), the outputs RASENO, CASEN are set
true (hi). If for RAM, BANKSEL = lo (address 8000-FFFF
unless VIDEO = hi, then address 8000-F800 unless 16K = hi
then address 8000-BFFF) RASENl, CASEN are set true (hi). If
for Video memory, (VIDEO = hi, address F800-FFFF), the
outputs are all false (lo). The input REFRESH sets all the
outputs false during its true time. The AND-OR gate U39 is
the RAM memory access decoder generating MEMREQ/, which
triggers the RAS-CAS timing sequencer U 6 1 , U 8 0 , and U81.
The equation for U39 is (MREQ*WRITE + MREQ*ROM*ROMAD*READ +
MREQ*RAM*READ). Basically, this allows write access to the
RAM memory for all addresses but limits the read accesses to
only those addresses not shadowed by the ROM memory if ROM
is true.
The RAM timing sequencer generates the RAS, CAS and MUXSEL
to read, write and refresh the dynamic RAM ICs. For the
lower memory bank RASO, MUXSEL and CAS are required; for the
upper bank RAS1, MUXSEL and CAS are needed. (RASENO and
RASENl never occur together). The fixed timing sequence is
generated by the delay line U80. When MEMREQ/ goes true
(lo), (and for instance, RASENO, CASEN are true) U81.6,
U62.6 are set lo, and U81.7 stays hi. U81.6 sets RASOP lo
and U62.6 starts a negative level through the delay line.
The 150 nanosecond tap clears U62.6, thereby creating a 150
ns negative pulse. This pulse, delayed 30 n s , =
MUXSEL/, which switches the address multiplexer from the row
address to the column address. The pulse delayed 60 ns sets
U62.7 or CASP lo. The pulse delayed 240 ns clears RASOP
(U62.7). CASP flip-flop U81.7 is cleared by the trailing
edge of MEMREQ/. This establishes a minimum length RAS*
(240 ns) to insure the minimum pre-charge time for the RAS
only REFRESH cycle to follow (if Ml cycle). Now, RASP (RAS
Prime) is ORed with (MREQ*REFRESH) (RAS refresh) and applied
to U82-U89 through damping resistor R 6 0 . CASP (CAS Prime)
is buffered to U63-U89 through damping resistor R59.
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