Tandy 6000 HD, Service Manual

Page: 172 / 416

Service Manual
TANDY 6000/6000-HD
TANDY COMPUTER PRODUCTS ------------------------------------------------------------------------
For the above example, the following equation applies:
If we want to Read the Status of Port FF, we activate the
FFRD* signal to enable the 3-state buffers LS240, U38. This
will produce the status of the KBIRQ*, the BLNKVID*, the
80*/40 character mode*, and the ENABLE RTC INT* as shown at
the inputs 2, 4, 6, and 8 of U38.
Other Blocks
The 3-state Buffers (U36, U37) are enabled by either the
Video Read (VRD) or Write* (WR*). VRD is the result of the
RD signal ANDed with MSP (Ul3 pins 11, 12, and 13). VWR* is
the output of WR NANDed with MSP (U2 pins 11, 12, and 13).
When the CPU wants to write data into the Video RAM, WR*
goes low (U36, U37 pin 1). When it does, a reading from the
Video RAM, VRD (high) is active (pin 15 of U36, U37). Test
points TP2 and TP24 will help detect if data is read from or
written into the Display RAM by the CPU.
The keyboard control consists of an LS74 Flip-Flop (U17,
pins 9, 11, and 12) showing the keyboard mode. That is,
when data is being clocked in from the keyboard, a busy
signal is sent to the system bus at the end of every word (8
bits of d a t a ) . A busy (active low) signal goes from pin 9
of U17 back to the keyboard processor, telling it to stop
sending data. Also, the same signal goes toward the CPU
under the name of Keyboard Interrupt Request (KBIRQ*),
telling it that a word of data is ready to be read. Data is
clocked serially out of the keyboard into the shift register
(U6) and then latched into the system data bus when FCRD*
port is activated. Note that when FCRD* is activated (low),
the Flip-Flop (U17 pins 11 and 12) becomes set and the
KBIRQ* or BUSY* signal goes high (disable). Now that the
keyboard logic does not receive the active busy signal, it
will start sending data again.
The timing diagram of Figure 7-14 shows how data leaves the
keyboard in serial fashion. Notice the narrower pulse
labeled End Of Data pulse. It is generated at the end of an
8 data bit sequence. Its rising edge latches a low to the
output o f U 1 7 p i n 9. T h i s 1ow signal (KBIRQ* or B U S Y * )
informs the CPU that a word is ready to be read. It also
prevents the keyboard from sending more data until the
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