Tandy 6000 HD, Service Manual

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Service Manual TANDY 6000/6000-HD
TAN D Y COMPUTER PRODUCTS ----------------------------------------------------------------------
7.2.7 MC68000 I/O Decoding and Strobes
The I/O devices in the MC68000 subsystem are memory-mapped
and consist of the:
Interrupt controller chip
Memory management registers
Z80A interrupt (NOT implemented in the Model II
upgrades)
All other I/O devices and peripherals in the TANDY
6000/6000-HD are still controlled by the Z80A CPU.
The main I/O decoding is managed by chip U48, which is the
I/O controller. The I/O controller interfaces the MC68000
CPU to the MC68000 subsystem I/O devices, thereby providing
all necessary signals.
Sheet 2 of the MC68000 CPU schematic should be referenced
unless otherwise noted. The current I/O devices are mapped
at address locations 7800D0H to 7800D7H. Address bits
KA20-KA22 are decoded by a 3 input AND gate (1/3 of UlO)
that generates the signal VMIIAD.
VMIIAD and mIO (KA19) are connected to the I/O controller
and generate the I/O signals during access to the memory
space 780000H to 78FFFFH. When an I/O access is executed,
R/W*, KA19, VMIIAD, AS*, and the 8 MHz CK start a 3 bit
internal counter. This counter is used to time the
assertion of B I O R Q * , B R D * , and B W R * , and IODTACK*.
R/W* and AS* determines the assertion of BRD* or BIOR*.
BIORQ* is used to enable a 1 of 8 decoder U41 that decodes
address bits KA1-KA7.
KA4, K A 6 , and KA7 are decoded by a 3-input AND gate, l/3rd
of U27, and the output is connected to the active-high
enable input U41 pin 6. KA5 enables the third enable input
U41 pin 4 when an active low occurs.
KA1-KA3 are decoded to determine the output of U32 that
selects the I/O device. Table 7-2 outlines the
memory-mapped I/O locations currently implemented in the
MC68000 subsystem. See Figure 7-7 for the timing
relationships of the I/O controller U48.
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