Tandy 6000 HD, Service Manual

Page: 126 / 416

Service Manual
TANDY 6000/6000-HD
TAN D Y COMPUTER PRODUCTS ----------------------------------------------------------------------
6. Interrupt Control
The CPU has two types of interrupts; maskable (INT/) and
non-maskable (NMI/). The non-maskable interrupt (bus name
NMIR Q * ) is a Method 1 type interrupt (see Z80
specification). The sources for this signal are on the BUS
only. Like the "wait" and "bus request" signals, the
sources apply their signal onto the bus through an
open-collector buffer and the CPU section provides the
pull-up resistor for the wired—OR output. At present, the
only source for this signal is the REAL TIME CLOCK on the
Video/Keyboard Interface PCB. The maskable interrupt
(INTRQ/) is a Mode 2 type interrupt. All sources are on a
daisy-chain priority scheme where interrupt requests from
all sources are ORed together but who gets to make the
request is established by the acknowledge from the CPU being
passed from the highest priority IC down until the requestor
stops it, preventing lower priority ICs from responding
(IEI,IEO). The requestors are divided into two groups;
internal (INTRQ/) from the BOARD, and external (INTRQ*) from
the bus. The priority scheme has the four Z80A functions on
the board assigned the highest priority with a descending
priority of CTC, SIO, DMA and PIO. The bus continues the
priority scheme and establishes priority by position
(provided a back plane with connectors is present) by
daisy-chaining the acknowledges IEIN* (IEI), IEOUT* (IEO).
If a board slot is empty, that stops the chain.
7.4.2 Memory Section
1. RAM
The RAM memory section consists of two sets of 8 dynamic RAM
ICs and an address multiplexer. The first or base set of
RAM (U82-U89) is 64K in size; the second set (U63-U70) is
either 16K or 64K in size. The RAM memory is divided into
32K size groups called Pages of which there can be as many
as 16 (0-15). See Table 7-6 for a memory map. Page 0 is
called the Base Page and is always available at address
0-32K (if LOW PAGE = low; if LOW PAGE = hi, address
32K-64K). The other Pages are selected one at a time by a
value (01-0F) at port FF and respond in the address range
32K-64K (if LOW PAGE = low; if = hi address 0-32K). The
addresses for dynamic RAMs require multiplexing. This is
done by U52, U53, and U79. The upper address bits are
combined with the lower address in pairs to form RAC*s.
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