Tandy 6000 HD, Service Manual

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Service Manual TANDY 6000/6000-HD
TAN D Y COMPUTER PRODUCTS ----------------------------------------------------------------------
The active-high state of DBTR enables the data drivers. It
follows, therefore, that the data receivers are disabled
when:
A read or write is in progress from the Interrupt
Controller chip (INTCS*)
A board interrupt acknowledge sequence is in progress
(PRIORINTAK *)
A write to external memory (R/W*) occurs
It should be noted that the CD control line overrides the
T/R* control line, and that both drivers and receivers are
disabled (tri-stated) if BGACK is asserted.
2. Address Lines
The MC68000 address lines are interfaced to the address bus
via tranceivers Ull, U28, and U30, which are the same type
used for the data lines. The CD control line ON Ull AND U28
is connected directly to ground, which always enables
address lines KAl-KAll, and KA20-KA23 to the address bus
unless BGACK* is active. The CD Input of U30 is controlled
by MMA which indicates if the MC68000 is in supervisor or
user mode. If it is in supervisor mode U30 is enabled and
KA12-KA19 is enabled to BA12-BA19. If it is in the user mode
U30 is disabled and BA12-BA19 is driven by the Memory
Management Circuitry. Refer to section 7.2.4. The direction
control line (T/R*) is switched by BGACK*, which indicates
who has bus mastership. If the MC68000 CPU is bus master,
then BGACK* is negated and the address lines are driven onto
the bus. If an external device is bus master, BGACK* will
be asserted and the address contained on the bus will be
gated onto the CPU address lines.
The CPU control lines may be divided into six major groups.
These are:
Memory Access Control Lines
Bus Arbitration Lines
Interrupt Priority Lines
Function Code Lines
MC68000 Peripheral Interface Lines
System Control Lines
Memory Access Control Lines
The memory access control lines include Address Strobe
(AS*), Lower Data Strobe (L D S * ), Upper Data Strobe (UDS*),
Read/Write (R/W*), and Data Transfer Acknowledge (DTACK*).
AS* indicates there is a valid address on the address lines
of the MC68000 CPU and it is connected directly to the
MC68000 subsystem devices.
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