Surface Concept DLD4040, Manual

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Delayline Detector DLD4040 Manual
DLD4040 R2.55 & R3.54 Manual | Surface Concept GmbH
11 List of Figure
Figure 1a: 0/0 position of the DLD R2.55 image (red dot).. .................................................................................................................................... 8
Figure 1b: 0/0 position of the DLD R3.54 image (red dot).. .................................................................................................................................... 8
Figure 2a: Connection scheme of the delayline detector R2.55 and readout package. ............................................................................... 9
Figure 2b: Connection scheme of the delayline detector R3.54 and readout package. ............................................................................... 9
Figure 3: Schematic sketch on voltage ramping during “Start-Up“ procedure. .............................................................................................. 14
Figure 4: Example for DLD image of accumulated dark counts. .......................................................................................................................... 15
Figure 5: Schematic sketch on voltage ramping with external reference voltage. ....................................................................................... 18
Figure 6: Schematic drawing of the principle of the 3D (x, y, t) delayline operation. ................................................................................... 21
Figure 7: Example of a partial overload (left) and a heavy (global) overload (right)... .................................................................................. 23
Figure 8: Example of an over voltage on the MCPs (left) and an under voltage at high count rates (right). ....................................... 24
Figure 9: Schematic orientation and naming of delaylines and DLD image . .. ................................................................................................ 25
Figure 10: Connection ports of the DLD4040 R2.55 (left) and the DLD4040 R3.54 (right). ........................................................................ 26
Figure 11: Internal connection of high voltage potentials (schematic). ............................................................................................................ 27
Figure 12: Layout of ACU 3.4.2. ......................................................................................................................................................................................... 29
Figure 13: Labeling of discriminator threshold and amplification regulators. ................................................................................................ 30
Figure 14: Typical gain degradation of MCPs as function of the extracted output charge. ....................................................................... 33
Figure 15: Schematic plot of increasing the operation voltage to compensate gain degradation over time as function of the
extracted charge (all values are only exemplary). ...................................................................................................................................................... 34
Figure 16: Example of MCP curve (for illustration only). ......................................................................................................................................... 35