Supero X7DWU, User Manual

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X7DWU User's Manual
C1/C2 Enhanced Mode (Available if supported by the CPU.)
Set to Enabled to enable Enhanced Halt (C1) State and Stop Clock (C2) State to
lower CPU voltage/frequency to prevent the processor from overheating. The op-
tions are Enabled and Disabled . P lease refer to Intel’s web site for details.)
Execute Disable Bit (Available when supported by the CPU.)
Set to Enabled to allow the processor to classify areas in memory where an ap-
plication code can execute and where it cannot, and thus preventing a worm or
a virus from inserting and creating a fl ood of codes to overwhelm the processor
or damage the system during an attack. The options are Disabled and Enabled.
For more information regarding this function, please refer to Intel's and Microsoft's
web sites.
Adjacent Cache Line Prefetch (Available when supported by the
CPU.)
The CPU fetches the cache line for 64 bytes if this option is set to Disabled . The
CPU fetches both cache lines for 128 bytes as comprised if Enabled. The default
settings are Disabled for the Intel 5100 Series Processors and Enable for the 5000
Series Processors.
Hardware Prefetcher (Available when supported by the CPU.)
Set to Enabled to activate the hardware components that are used in conjunction
with software programs to prefetch data in order to shorten execution cycles and
maximize data processing effi ciency. The options are Disabled and Enabled .
Set Maximum Ext. CPUID=3
When set to Enabled, the Maximum Extended CPUID will be set to 3. The options
are Disabled and Enabled.
Direct Cache Access (Available when supported by the CPU.)
Set to Enable to route inbound network IO traffi c directly into processor caches
to reduce memory latency and improve network performance. The options are
Disabled and Enabled.
DCA Delay Clocks (*Available if supported by the CPU.)
This feature allows the user to set the clock delay setting from snoop to prefetch
for Direct Cache Access. Select a setting from 8 (bus cycles) to 120 (bus cycles)
(in 8-cycle increment). The default setting is 32 (bus cycles).