Supero SuperWorkstation 5033C-T, User Manual

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UPER
W
ORKSTATION 5033C-T User's Manual
1-2 Motherboard Features
At the heart of the SuperWorkstation 5033C-T lies the P4SCT+II, a single pro-
cessor motherboard designed to provide maximum performance. Below are the
main features of the P4SCT+II.
Chipset Overview
The P4SCT+II is based on Intel’s 875P chipset. See Figure 1-1 for a block
diagram of the chipset. The 875P chipset is made up of two main components:
The Memory Controller Hub (MCH)
The I/O Controller Hub (6300ESB)
Memory Controller Hub (MCH)
The MCH includes the host (CPU) interface, memory interface, I/O controller hub
interface, CSA interface and AGP interface. It contains advanced power manage-
ment logic and supports dual-channel (interleaved) DDR memory, providing band-
width of up to 6.4 GB/s using DDR-400 SDRAM. The MCH supports the following
front side bus/memory bus configurations: 800 MHz FSB with a 400/333 memory
interface, a 533 MHz FSB with a 333/266 memory interface and a 400 MHz FSB
with a 266 MHz memory interface. The AGP interface supports 8x data transfers
and operates at a peak bandwidth of 2.1 GB/s. The CSA (Communications
Streaming Architecture) interface connects the MCH to a Gigabit Ethernet con-
troller.
I/O Controller Hub (6300ESB)
The 6300ESB ICH controller hub provides the I/O subsystem with access to the rest
of the system. It integrates two Serial ATA (SATA) host controllers, a dual-channel
Ultra ATA/100 bus master IDE controller, an SMBus 2.0 controller, the LPC/Flash
BIOS interface, the PCI-X (66MHz) 1.0 interface, the PCI 2.2 interface and the
System Management Controller.