Supero SuperServer 5012B-6, User Manual

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UPER
S
ERVER 5012B-6/5012B-E Manual
1-4
1-3 Mainboard Features
At the heart of the SuperServer 5012B-6/5012B-E lies the P4SBR/P4SBE, a
single processor motherboard designed to provide maximum performance.
Below are the main features of the P4SBR/P4SBE.
Chipset Overview
Intel’s 845 chipset is made up of three main components:
The 82845 Memory Controller Hub (MCH) with an Accelerated Hub Architec-
ture (AHA) bus.
The 82801 BA I/O Controller Hub (ICH2) with an AHA bus.
The 82802 AB Firmware Hub (FWH).
Memory Controller Hub (MCH)
The MCH includes the host (CPU) interface, SDRAM interface, ICH2 inter-
face and 4xAGP interface for the 845 chipset. It contains advanced power
management logic and supports three DIMMS for up to 3 GB of unbuffered
SDRAM. The AGP 2.0 interface supports 4x data transfers and operates at
a peak bandwidth of 1.6 GB. The MCH host interface bus runs at 400 MHz.
I/O Controller Hub (ICH2)
The I/O Controller Hub (ICH2) subsystem on the P4SBR/P4SBE integrates
many of the input/output functions of the 845 chipset, including a dual chan-
nel ATA/100 Bus Master IDE controller and two USB controllers that offer
24 Mbps of bandwidth across four ports. It also provides the interface to
the PCI Bus and communicates with the MCH over a dedicated hub interface
bus -- the AHA. The ICH2 also features an enhanced AC97 interface that
supports full surround sound for the Dolby Digital Audio used on DVDs.
Firmware Hub (FWH)
The FWH is a component that brings added security and manageability to
the PC platform infrastructure. The FWH stores the system BIOS and video
BIOS to eliminate a redundant nonvolatile memory component.