Supero SUPER 370SBA, User Manual

Page: 23 / 92

Chapter 1: Introduction
1-13
1-3 Chipset Overview
440BX Chipset
The 440BX chipset, developed by Intel, is the ultimate processor platform
targeted for 3D graphics and multimedia applications. Along with System-to-
PCI bridge integrated with optimized DRAM controller and data path, the
chipset introduces the Accelerated Graphics Port (AGP) interface. AGP is a
high performance, component level interconnect targeted at 3D applications
and is based on a set of performance enhancements to PCI. The I/O sub-
system portion of the 440BX platform is based on the PIIX4E, a highly inte-
grated version of Intel's PCI-to-ISA bridge family.
The PCI/AGP and system bus interface controller (82443BX) supports one
Celeron processor. It provides an optimized 72-bit DRAM interface (64-bit
data plus ECC). This interface supports 3.3V DRAM technologies. The con-
troller provides the interface to a PCI bus operating at 33 MHz. This interface
implementation is compliant with the PCI Rev 2.1 Specification. The AGP
interface is based on the AGP Specification Rev 1.0. It can support up to 133
MHz (532 MB/s) data transfer rates.
440LX Chipset
The 440LX chipset, developed by Intel, is a high-performance processor
platform targeted for existing 3D graphics and multimedia applications.
Along with System-to-PCI bridge integrated with optimized DRAM controller
and data path, the chipset introduced the Accelerated Graphics Port (AGP)
interface. AGP is a high performance, component level interconnect
targeted at 3D applications and is based on a set of performance enhance-
ments to PCI. The I/O subsystem portion of the 440LX platform is based
on the PIIX4, a highly integrated version of Intel's PCI-to-ISA bridge family.
The 440LX PCI/AGP Controller (PAC) system bus interface supports one
Celeron processor. It provides an optimized 72-bit DRAM interface (64-bit
data plus ECC). This interface supports 3.3V DRAM technologies. The
PAC provides the interface to a PCI bus operating at 33 MHz. This
interface implementation is compliant with the PCI Rev 2.1 Specification.
The AGP interface is based on the AGP Specification Rev 1.0. It can
support up to 133 MHz (532 MB/s) data transfer rates.