66 STC12C5Axx
Technical Summary
Power Management
IDLE Mode
An instruction setting
PCON
.0 causes the device go into the idle mode, the internal clock is
gated off to the CPU but not to the interrupt, timer, PCA, SPI, ADC, WDT and serial port
functions.
There are two ways to terminate the idle. Activation of any enabled interrupt will cause
PCON
.0 to be cleared by hardware, terminating the idle mode. The interrupt will be serviced,
and following RETI instruction, the next instruction to be executed will be the one following the
instruction that puts the device into idle. Another way to wake-up from idle is to pull pin RST
high to generate internal hardware reset.
Save Power Consumption under IDLE Mode
A clock divider(CLKDIV) associated with idle mode is used to slow down the system clock
source in order to save power in advance. Everybody knows that slower the clock oscillates,
less power consumed. Software could program this clock divider register prior to enter the idle
mode. When the chip enters the idle mode, the clock is switched to the divider. When the
chip exits the idle mode, clocking will return to the original clock behavior.
SFR: CLK_DIV
(
Power Control )
Read/Write
Address:
0X97H
Default: XXXX-X000
Bit
7
6
5
4
3
2
1
0
Name
CKS2
CKS1
CKS0
{CKS2, CKS1, CKS0}:
Clock selector under idle mode
{0, 0,0}
: = (default)
In idle mode, clock is not divided (default state)
{0, 0, 1}
: =
In idle mode, clock is divided by 2
{0, 1, 0}
: =
In idle mode, clock is divided by 4
{0, 1, 1}
: =
In idle mode, clock is divided by 8
{1, 0,0}
: =
In idle mode, clock is divided by 16
{1, 0, 1}
: =
In idle mode, clock is divided by 32
{1, 1, 0}
: =
In idle mode, clock is divided by 64
{1, 1, 1}
: =
In idle mode, clock is divided by 128
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