STC STC12C5A Series Manual Download Page 70

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70 STC12C5Axx

Technical Summary

Mode Selection

To Operate

0 0

Standby

0 1

AP-memory read

1 0

AP-memory/Data-flash program

1 1

AP-memory/Data-flash page erase

SFR:

IAP_TRIG (ISP Sequential Command register to trigger ISP/IAP operation)

Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0

ISP-Command / Device ID

SFR:

IAP_CONTR (IAP Control register)

Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0

IAPEN SWBS SWRST

CFAIL

WAIT

IAPEN: =

Determine if to Enable ISP/IAP functionality

: =

Disable ISP program to change flash.

: =

Enable ISP program to change flash.

SWBS: =

Software Boot entrance Selector

: =

Boot from main-memory.

: =

Boot from ISP memory.

Note: This bit will be loaded with HWBS(OR0.3) after power-up moment.

SWRST: =

Software Reset trigger

Setting this bit will cause the device reset.

CFAIL: =

ISP/IAP Command Fail flag

: =

The last ISP/IAP command has finished successfully.

: =

The last ISP/IAP command fails. It could be caused since the

access of flash memory

was inhibited.

WAIT: =

Waiting time selection while the flash is busy.

CPU Wait time (Oscillator cycle)

IAP_CONTR[2:0] Page

Erase

Program

Read

Recommended

System clock

0 0 0

672384

1760

30M~24M

0 0 1

504288

1320

24M~20M

0 1 0

420240

1100

20M~12M

0 1 1

252144

660

12M~6M

1 0 0

126072

330

6M~3M

1 0 1

63036

165

3M~2M

1 1 0

42024

110

2M~1M

1 1 1

21012

< 1M

Notice

: Software reset actions could reset other SFR, but it never influences bits IAPEN

and SWBS. The ISPEN and SWBS only will be reset by power-up action, while
not software reset.

http://www.DataSheet4U.net/

datasheet pdf - http://www.DataSheet4U.net/

Summary of Contents for STC12C5A Series

Page 1: ...n 17 I O Port Configuration 17 Timer Counter 21 BAUD RATE GENERATOR BRT 25 Interrupt 27 Watch Dog Timer 34 Universal Asynchronous Serial Port UART 36 Secondary Universal Asynchronous Serial Port S2 40 Programmable Counter Array PCA 45 Serial Peripheral Interface SPI 55 Analog to Digital Converter 63 Power Management 66 In System Programming and In Application Programming 69 In System Programming I...

Page 2: ...2 STC12C5Axx Technical Summary Version History 78 http www DataSheet4U net datasheet pdf http www DataSheet4U net ...

Page 3: ...2 with self baud rate generator z One enhanced UART with automatic address recognition and frame error detection z SPI Master Slave communication interface z 15 bits Watch Dog Timer with 8 bit pre scalar one time enabled z Two Channel Programmable Counter Array PCA z 10 bit Analog to Digital Converter ADC z Power control idle mode and power down mode Power down can be woken up through INT0 and INT...

Page 4: ...0Bits Analog To Digital Converter make it easy to sensing the environment or implement a set of scan keys in low cost The UART interfaces make the device convenient to communicate with the peripheral component say talking to a personal computer via RS 232 port or communicating with a serial memory The Pulse Width Modulator PWM and Programmable Counter Array PCA make the device to drive the periphe...

Page 5: ...tten into Port1 the strong output driving PMOS only turn on two period and then the weak pull up resistance keep the port high ADCn Analog to Digital Converter Input P2 0 P2 7 21 28 24 31 18 25 19 23 26 28 Port2 Port2 is an 8 bit bi directional I O port with pull up resistance Except being as GPIO Port2 emits the high order address byte during accessing to external program and data memory P3 0 RXD...

Page 6: ...ALE Address Latch EX_LVD External Low Voltage Reset Detector RESET 9 10 4 5 RESET A high on this pin for at least two machine cycles will reset the device P5 0 P5 1 P5 2 P5 3 24 25 48 1 Port5 Port4 are extended I O ports such like Port1 It can be available only on 48L LQFP XTAL1 19 21 15 16 Crystal1 Input to the inverting oscillator amplifier XTAL2 18 20 14 15 Crystal2 Output from the inverting am...

Page 7: ...1 GND P0 1 AD1 P0 0 AD0 VDD 1 20 21 40 PDIP 40 P1 1 STC12C5Axx MOSI P1 5 MISO P1 6 SCLK P1 7 RXD P3 0 RST P4 7 TXD P3 1 INT0 P3 2 INT1 P3 3 CLKOUT0 T0 P3 4 CLKOUT1 T1 P3 5 P3 6 WR P3 7 RD XTAL2 XTAL1 GND P4 0 SS P2 0 A8 P2 1 A9 P2 2 A10 P2 3 A11 P2 4 A12 P0 4 AD4 P2 5 A13 SS CCP1 P1 4 CCP0 P1 3 ECI P1 2 CLKOUT2 P1 0 MISO CCP0 P4 2 VDD AD0 P0 0 AD1 P0 1 AD2 P0 2 AD3 P0 3 1 SCLK CCP1 P4 3 STC12C5Axx...

Page 8: ... 7 A15 P2 6 A14 P2 5 A13 SS CCP1 P1 4 CCP0 P1 3 ECI P1 2 P1 1 CLKOUT2 P1 0 MISO CCP0 P4 2 VDD AD0 P0 0 AD1 P0 1 AD2 P0 2 AD3 P0 3 1 7 40 SCLK CCP1 P4 3 P4 1 ECI MOSI 18 29 STC12C5Axx PLCC 44 MOSI P1 5 MISO P1 6 SCLK P1 7 RXD P3 0 RST P4 7 TXD P3 1 INT0 P3 2 INT1 P3 3 CLKOUT0 T0 P3 4 CLKOUT1 T1 P3 5 P3 6 WR P3 7 RD XTAL2 XTAL1 GND P4 0 SS P 0 A8 P2 1 A9 P2 2 A10 P2 3 A11 P2 4 A12 P0 4 AD4 P2 5 A13 ...

Page 9: ...STC12C5Axx Technical Summary 9 Block Diagram ALU http www DataSheet4U net datasheet pdf http www DataSheet4U net ...

Page 10: ... C0 P4 WDT_CONTR IAP_DATA IAP_ADDRH IAP_ADDRL IAP_CMD IAP_TRIG IAP_CONTR B8 IP SADEN P4SW ADC_CONTR ADC_RES ADC_RESL B0 P3 P3M1 P3M0 P4M1 P4M0 IP2 IP2H IPHIPH A8 IE SADDR A0 P2 BUS_SPEED AUXR1 TEST_WDT 98 SCON SBUF S2CON S2SBUF BRT P1ASF 90 P1 P1M1 P1M0 P0M1 P0M0 P2M1 P2M0 CLK_DIV 88 TCON TMOD TL0 TL1 TH0 TH1 AUXR WAKE_CLK0 80 P0 SP DPL DPH PCON Write Only http www DataSheet4U net datasheet pdf ht...

Page 11: ... 0M0 00000000B CLK_DIV 97H CLKS2 CLKS1 CLKS0 xxxxx000B SCON 98H SM0 SM1 SM2 REN TXSTS TISEL TI RI 00000000B SBUF 99H SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 xxxxxxxxB S2CON 9AH S2SM0 S2SM1 S2SM2 S2REN S2TB8 S2RB8 S2TI S2RI 00000000B S2SBUF 9BH S2D7 S2D6 S2D5 S2D4 S2D3 S2D2 S2D1 S2D0 xxxxxxxxB BRT 9CH 00000000B P1SF 9DH P1 7ASF P1 6ASF P1 5ASF P1 4ASF P1 3ASF P1 2ASF P1 1ASF P1 0ASF 00000000B P2 A0H P2 7 P...

Page 12: ... xxxx0000B P5M0 CAH P5 7M0 P5 6M0 P5 5M0 P5 4M0 P5 3M0 P5 2M0 P5 1M0 P5 0M0 xxxx0000B SPSTAT CDH SPIF WCOL 00xxxxxxB SPCTL CEH SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPR0 00000100B SPDAT CFH 0000000B PSW D0H CY AC F0 RS1 RS0 OV P 00000000B CCON D8H CF CR CCF1 CCF0 00xxxx00B CMOD D9H CIDL CPS2 CPS1 CPS0 ECF 0xxx0000B CCAPM0 DAH ECOMO CAPP0 CAPN0 MAT0 TOG0 PWM0 ECCF0 x0000000B CCAPM1 DBH ECOM1 CAPP1 CAP...

Page 13: ...or DPTR instructions which are named external or auxiliary RAM None of P0 status and P2 status will be affected during MOVX instruction A control bit EXTRAM located in SFR AUXR 1 register is to control access of auxiliary RAM When set disable the access of auxiliary RAM When clear EXTRAM 0 this auxiliary RAM is the default target for the address range from 0x0000 to 0x03FF If EXTRAM 0 and the targ...

Page 14: ... flash for both storage of application AP program and In System Program ISP code even he can configure the flash for storage of AP ISP and In Application Program IAP memory If there is requirement from the user s application program to store nonvolatile parameters the user can allocate part of the embedded flash as IAP memory by Part No http www DataSheet4U net datasheet pdf http www DataSheet4U n...

Page 15: ...erly to conform to the read write requirements of the external data memory being used BUS_SPEED Address A1H External Access Stretch Register BUS_SPEED register Read Write Address 0XA1H Default XX10 X011 Bit 7 6 5 4 3 2 1 0 Name ALES1 ALES0 RWS2 RWS1 RWS0 Note The reset value for BUS_SPEED is 00100011b 0x23 That is ALES1 ALES0 1 0 and RWS2 RWS1 RWS0 0 1 1 ALES1 ALES0 00 No stretch the P0 s address ...

Page 16: ...retched the MOVX read write pulse is 5 clock cycles 101 5 clocks stretched the MOVX read write pulse is 6 clock cycles 110 6 clocks stretched the MOVX read write pulse is 7 clock cycles 111 7 clocks stretched the MOVX read write pulse is 8 clock cycles http www DataSheet4U net datasheet pdf http www DataSheet4U net ...

Page 17: ...ion registers designed to configure those I O ports SFR P0M0 P0 Configuration 0 Read Write Address 0X94H Default 0000 0000 Bit 7 6 5 4 3 2 1 0 Name P0M0 7 P0M0 6 P0M0 5 P0M0 4 P0M0 3 P0M0 2 P0M0 1 P0M0 0 SFR P0M1 P0 Configuration 1 Read Write Address 0X93H Default 0000 0000 Bit 7 6 5 4 3 2 1 0 Name P0M1 7 P0M1 6 P0M1 5 P0M1 4 P0M1 3 P0M1 2 P0M1 1 P0M1 0 SFR P1M0 P1 Configuration 0 Read Write Addre...

Page 18: ... 3 2 1 0 Name P4M1 7 P4M1 6 P4M1 5 P4M1 4 P4M1 3 P4M1 2 P4M1 1 P4M1 0 SFR P5M0 P5 Configuration 0 Read Write Address 0XCAH Default 0000 0000 Bit 7 6 5 4 3 2 1 0 Name P5M0 7 P5M0 6 P5M0 5 P5M0 4 P5M0 3 P5M0 2 P5M0 1 P5M0 0 SFR P5M1 P5 Configuration 1 Read Write Address 0XC9H Default 0000 0000 Bit 7 6 5 4 3 2 1 0 Name P5M1 7 P5M1 6 P5M1 5 P5M1 4 P5M1 3 P5M1 2 P5M1 1 P5M1 0 Configuration of I O port ...

Page 19: ... up called the weak pull up is turned on when the port register for the pin contains a logic 1 and the pin itself is also at a logic 1 level This pull up provides the primary source current for a quasi bidirectional pin that is outputting a 1 If this pin is pulled low by the external device this weak pull up turns off and only the very weak pull up remains on In order to pull the pin low under the...

Page 20: ... mode Port pin Input data Port latch data Input only Mode The input only configuration is a Schmitt triggered input without any pull up resistors on the pin Port pin Input data Push pull Output The push pull output configuration has the same pull down structure as both the open drain and the quasi bidirectional output modes but provides a continuous strong pull up when the port register contains a...

Page 21: ...TMOD TCON The user also should take a glace of SFR AUXR which decide the frequency of the clock source driving the T0 and T1 SFR TMOD Timer Mode Control Register Read Write Address 0X89H Default 0000 0000 Bit 7 6 5 4 3 2 1 0 For Timer 1 Only For Timer 0 Only Name GATE C T M1 M0 GATE C T M1 M0 GATE Gating control 0 default Timer x is enabled whenever TRx control bit is set 1 Timer Counter x is enab...

Page 22: ... T0 counting IE1 External Interrupt 1 flag This bit is automatically set by hardware on interrupt from the external interrupt 1 and will be automatically cleared by hardware when the processor vectors to the interrupt routine IT1 Interrupt 1 type control bit 0 default Set the interrupt 1 triggered by low duty from pin EX1 1 Set the interrupt 1 triggered by negative falling edge from pin EX1 IE0 Ex...

Page 23: ...the oscillator frequency It will drive the T1 faster than a traditional 80C51 MCU UARTM0X6 Baud rate selector of UART while it is working under Mode 0 0 default Set the baud rate of the UART functional block as oscillator frequency divided by 12 It will compatible to the traditional 80C51 MCU 1 Set the baud rate of the UART functional block as oscillator frequency divided by 2 It will transmit rec...

Page 24: ...ither GATE 0 or INTx 1 Mode 0 operation is the same for Timer0 and Timer1 Mode 1 Mode1 is the same as Mode0 except that the timer register is being run with all 16 bits Mode 2 Mode 2 configures the timer register as an 8 bit counter TLx with automatic reload Overflow from TLx does not only set TFx but also reloads TLx with the content of THx which is determined by user s program The reload leaves ...

Page 25: ...unter and take over the use of TR1 TF1 from Timer1 TH0 now controls the Timer1 interrupt BAUD RATE GENERATOR BRT BAUD RATE GENERATOR BRT Baud Rate Generator and P1 0 P4 1 programmable clock output 0 1 Sampled T0 pin 0 1 GATE INT0 TR0 TL0 7 0 TF0 Interrupt C T OSC 12 0 1 OSC AUXR x 0 1 TH0 7 0 TF1 Interrupt TR1 OSC 12 0 1 OSC AUXR x BRTR Fosc 12 8 bit timer Overflow BRT To UART Baud Rate Generator ...

Page 26: ...AKE_CLKO is set BRT timer overflow pulse will toggle P1 0 or P4 1 latch to generate a 50 duty clock The frequency of clock out is as following BRT timer overflow rate 256 BRT Fosc 256 BRT Fosc 12 or P1 0 P4 1 Clock output frequency 256 BRT Fosc 2 256 BRT Fosc 24 or http www DataSheet4U net datasheet pdf http www DataSheet4U net ...

Page 27: ...t INT0 and INT1 can each be either level activated or transition activated depending on bits IT0 and IT1 in register TCON The flags that actually generate these interrupts are bits IE0 and IE1 in TCON When an external interrupt is generated the flag that generated it is cleared by the hardware when the service routine is vectored to only if the interrupt was transition activated otherwise the exte...

Page 28: ...t blocked by any of the following conditions The 2BH interrupt is shared by the logical 1 of ADC interrupt and interrupt Neither of these flags is cleared by hardware when the service routine is vectored to The service routine should poll them to determine which one to request service and it will be cleared by software The 4BH interrupt is shared by the logical 1 of SPI interrupt and interrupt Nei...

Page 29: ...ectoring into any service routine Condition 3 ensures that if the instruction in progress is RETI or any access to SFRs IE IP IP2 IPH or IP2H then at least one or more instruction will be executed before any interrupt is vectored to The following content describes several SFR related to interrupt mechanism SFR PSW Program Status Word Read Write Address 0XD0H Default XXXX XX00 Bit 7 6 5 4 3 2 1 0 N...

Page 30: ... Disable 1 Enable EADC Interrupt controller of A D Converter ADC 0 default Disable 1 Enable ES Interrupt controller of Universal Asynchronous Receiver Transmitter UART 0 default Disable 1 Enable ET1 Interrupt controller of Timer 1 interrupt 0 default Disable 1 Enable EX1 Interrupt controller of external interrupt 1 0 default Disable 1 Enable ET0 Interrupt controller of Timer 0 interrupt 0 default ...

Page 31: ...timer0 interrupt higher PX0 If set Set priority for external interrupt 0 higher SFR IPH Interrupt Priority High Read Write Address 0XB7H Default 0000 0000 Bit 7 6 5 4 3 2 1 0 Name PPCAH PLVDH PADCH PSH PT1H PX1H PT0H PX0H PPCAH If set Set priority for PCA interrupt higher PLVDH If set Set priority for Low Voltage interrupt higher PADC If set Set priority for ADC interrupt higher PSH If set Set pri...

Page 32: ...rsion A1 SFR IP2 Interrupt Priority High Read Write Address 0XB6H Default 0000 0000 Bit 7 6 5 4 3 2 1 0 Name PSPI PS2 SFR IP2H Interrupt Priority High Read Write Address 0XB7H Default 0000 0000 Bit 7 6 5 4 3 2 1 0 Name PSPIH PS2H IP and IPH are combined to form 4 level priority interrupt as the following table IPH x IP x Priority Level 11 1 highest 10 2 01 3 00 4 http www DataSheet4U net datasheet...

Page 33: ...Highest Priority Level Interrupt Lowest Priority Level Interrupt Interrupt Polling Sequenc e Global Enable IE 7 Individual Enable CF ECF CCF1 ECCF1 CCF0 ECCF0 CCF2 ECCF2 IE 0 IE 1 IE 2 IE 3 IE 4 IE 5 IE2 1 IE 5 ECF IE2 0 IE 6 TF2 EXF2 SPIF ADC_FLAG S2RI S2TI EPOF POF ELVD LVDF http www DataSheet4U net datasheet pdf http www DataSheet4U net ...

Page 34: ...t PS2 PS1 PS0 EN_ WDT CLR_ WDT IDL_ WDT WDT_ FLAG 1 256 1 128 1 64 1 32 1 16 1 8 1 4 1 2 8 bit prescalar 15 bit timer IDLE Fosc 12 WDT_CONTR To make good use of the watch dog timer the user should take notice on SFR WDT_CONTR SFR WDT_CONTR WDT Control Register C1H Read Write Address 0XC1H Default 0000 0000 Bit 7 6 5 4 3 2 1 0 Name WDT_FLAG EN_WDT CLR_WDT IDL_WDT PS2 PS1 PS0 WDT_FLAG When WDT overf...

Page 35: ...d happen PS2 PS1 PS0 selector of the WDT pre scalar output 0 0 0 set the pre scaling value 2 0 0 1 set the pre scaling value 4 0 1 0 set the pre scaling value 8 0 1 1 set the pre scaling value 16 1 0 0 set the pre scaling value 32 1 0 1 set the pre scaling value 64 1 1 0 set the pre scaling value 128 1 1 1 set the pre scaling value 256 http www DataSheet4U net datasheet pdf http www DataSheet4U ne...

Page 36: ...on An 8 bit data is serially transmitted received with LSB first The baud rate is fixed at 1 12 the oscillator frequency If AUXR 5 URM0X6 is set the baud rate is 1 2 oscillator frequency Mode1 A 10 bits data is serially transmitted through pin TXD or received through pin RXD The frame data includes a start bit 0 8 data bits and a stop bit 1 After finishing a receiving the device will keep the stop...

Page 37: ...erating mode of the serial port 0 0 set the serial port operate under Mode 0 0 1 set the serial port operate under Mode 1 1 0 set the serial port operate under Mode 2 1 1 set the serial port operate under Mode 3 SM2 Enable the automatic address recognition feature in mode 2 and 3 If SM2 1 RI will not be set unless the received 9th data bit is 1 indicating an address and the received byte is a Give...

Page 38: ...38 STC12C5Axx Technical Summary bit RI Receive done flag After reception has been finished the hardware will set this bit http www DataSheet4U net datasheet pdf http www DataSheet4U net ...

Page 39: ...both of them Finally the hardware will make use of these two SFR to generate a compared byte The formula specifies as following For example Set SADDR 11000000b Set SADEN 11111101b Ö The achieved Compared Byte will be 110000x0 x means don t care For another example Set SADDR 11100000b Set SADEN 11111010b Ö The achieved Compared Byte will be 11100x0x After the generic Compared Byte has been worked o...

Page 40: ...e transmitted received with the LSB first The baud rate is fixed at 1 12 the oscillator frequency Regardless of baud rate generation the operation in Mode 0 for S2 UART is the same as the major UART in Mode 0 Mode1 10 bits are transmitted through pin TXD2 or received through pin RXD2 The frame data includes a start bit 0 8 data bits and a stop bit 1 One receive the stop bit goes into S2RB8 in SFR ...

Page 41: ...perate under Mode 1 8 bit UART 1 0 set the serial port operate under Mode 2 9 bit UART 1 1 set the serial port operate under Mode 3 9 bit UART S2SM2 Enable the automatic address recognition feature in mode 2 and 3 If SM2 1 RI will not be set unless the received 9th data bit is 1 indicating an address and the received byte is a Given or Broadcast address In mode1 if SM2 1 then RI will not be set un...

Page 42: ...R AUXR Read Write Address 0x9BH Default 0000 0000 Bit 7 6 5 4 3 2 1 0 Name T0x12 T1x12 UARTM0X6 BRTR S2SMOD BRTX12 EXTRAM S1BRS T0X12 Set this bit to set the clock source for timer 0 is Fosc or clear it to set the clock source for timer 0 as Fosc 12 T1X12 Set this bit to set the clock source for timer 0 is Fosc or clear it to set the clock source for timer 1 as Fosc 12 UARTM0x6 Set this bit to set...

Page 43: ... PCA WAKEUP RXD_PIN_ IE T1_PIN_ IE T0_PIN_ IE LVD_ WAKE BRTCLKO T1CLKO T0CLKO WAKEUP If this bit has been enabled the PCA interrupt can wake up the device from power down mode RXD_PIN_IE If this bit has been enabled the RXD interrupt can wake up the device from power down mode T1_PIN_IE If this bit has been enabled the Timer 1 interrupt can wake up the device from power down mode T0_PIN_IE If this...

Page 44: ...tput on P3 5 The frequency of the output clock will be set as Timer 1 overflow rate 2 TCLKO Setting this bit can enable timer 0 clock output on P3 4 The frequency of the output clock will be set as Timer 0 overflow rate 2 http www DataSheet4U net datasheet pdf http www DataSheet4U net ...

Page 45: ...A Timer Counter 16 Bit P1 3 CEX0 PCA0 PWM0 P1 4 CEX1 PCA1 PWM1 Programmable Counter Array In the CMOD SFR there are two additional bits associated with the PCA On of them is CIDL which determines if to stop the PCA while the MCU is put under idle the other bit is ECF which controls if to pass the interrupt from PCA into the MCU The CCON SFR contains the run control bit for PCA and several flags fo...

Page 46: ... of the PCA counter while the MCU is put under idle state CPS1 CPS0 Used to select the clocking source for PCA counter 0 0 set the frequency of the PCA counter clock source as oscillator s frequency over 12 0 1 set the frequency of the PCA counter clock source as oscillator s frequency over 2 1 0 set the PCA counter clock source as Timer 0 overflow 1 1 set the PCA counter clock source as pin ECI p...

Page 47: ...dware itself when a match or capture from module 0 occurs It can be cleared by software program Each module in the PCA has a special function register associated with it CCAPM0 for module0 and CCAPM1 for module 1 The register contains the bits that control the mode in which each module will operate The ECCFn bit controls if to pass the interrupt from CCFn flag in the CCON SFR to the MCU when a mat...

Page 48: ...ite Address 0XEAH Default 0000 0000 Bit 7 6 5 4 3 2 1 0 Name SFR CCAP0H High byte of PCA module 0 Compare Capture register Read Write Address 0XFAH Default 0000 0000 Bit 7 6 5 4 3 2 1 0 Name SFR CCAP1L Low byte of PCA module 1 Compare Capture register Read Write Address 0XEBH Default 0000 0000 Bit 7 6 5 4 3 2 1 0 Name SFR CCAP1H High byte of PCA module 1 Compare Capture register Read Write Address...

Page 49: ...the PCA counter on CAPPn posedge 1 configure the module n s register to latch the PCA counter on CAPPn posedge CAPNn configure the module n s register to latch the PCA counter on Negative edge of EXIn or not 0 default configure the module n s register not to latch the PCA counter on pin CAPPn negedge 1 configure the module n s register to latch the PCA counter on pin CAPPn negedge MATn used to det...

Page 50: ...chnical Summary Inhibit the PWM functionality from module n output to pin PWMn 1 Enable the pin PWMn as the output of the PWM functionality from module n http www DataSheet4U net datasheet pdf http www DataSheet4U net ...

Page 51: ... 1 0 X 16 bit High Speed Output 1 0 0 0 0 1 0 8 bit PWM PCA Capture Mode To use one of the PCA modules in the capture mode one or both of bits CAPPn and CAPNn in SFR CCAPMn should be set The external CEXn input for the module is sampled for a transition When a valid transition occurs the PCA hardware loads the value of the PCA counter register CH and CL into the module s capture registers CCAPnH a...

Page 52: ... CCAPnL 7 0 and bits EPCnL in SFR PCAPWMn When the value of the SFR CL is less than the value in the module s EPCnL CCAPnL 7 0 the output will be low When it is equal to or greater than the output will be high When CL overflows from FFH to 00H EPCnL CCAPnL 7 0 is reloaded with the value in EPCnH CCAPnH 7 0 That allows smoothly updating the PWM duty without glitches The bits PWMn and ECOMn bits in ...

Page 53: ...arator 0 0 CH CL MATCH 0 0 Enable 0 1 Write to CCAPnL Write to CCAPnH To CCFn CCAPnH CCAPnL TOGn PWMn ECCFn ECOMn CAPPn CAPNn MATn CCAPMn CCF1 CCF0 CR CF CCON PCA interrupt PCA High Speed Ouput Mode 16 bit comparator 1 0 CH CL MATCH 0 0 Enable 0 1 Write to CCAPnL Write to CCAPnH To CCFn CEXn Toggle http www DataSheet4U net datasheet pdf http www DataSheet4U net ...

Page 54: ...APnL EPCnL 9 BIT COMPARATOR CL 0 CL overflow ECOMn CAPPn CAPNn MATn TOGn PW Mn ECCFn 0 0 0 0 0 Enable 0 1 CEXn CCAPM n PCA PW M mode 0 CL 7 0 EPCnL CCAPnL 7 0 0 CL 7 0 EPCnL CCAPnL 7 0 http www DataSheet4U net datasheet pdf http www DataSheet4U net ...

Page 55: ...to configure the SPI to run under Master or Slave mode Data flows from master to slave via MOSI Master Out Slave In pin and flows from slave to master via MISO Master In Slave Out pin The SCLK plays as an output pin when the device works under Master mode while as an input pin when the device works under Slave mode If the SPI system is disabled i e SPEN SPCTL 6 0 these pins are configured as gener...

Page 56: ...e Address 0X85H Default 0000 0000 Bit 7 6 5 4 3 2 1 0 Name SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPR0 SSIG used to determine if Ignore the pin SS 0 default Reserve the function of pin SS 1 Ignore the SS pin function SPEN Enable the SPI 0 default Disable the SPI function All related pins play as general purposed I O ports 1 Enable the SPI function DORD Data Order 0 default Transmit Receive the MSB of ...

Page 57: ...s the frequency of the clock source over 64 1 1 Set the clock rate of the SPI as the frequency of the clock source over 128 There are two extra SFRs make relation with SPI application SFR SPDAT SPI Data register Read Write Address 0X86H Default 0000 0000 Bit 7 6 5 4 3 2 1 0 Name The SFR SPDAT holds the data to be transmitted or the data received SFR SPSTAT SPI STATe register Read Write Address 0X8...

Page 58: ... MOSI SPICLK Remark 0 X X X SPI disable GPI O GPI O GPI O SPI is disabled 1 0 0 0 Active Salve output input input Selected as slave 1 0 1 0 InActive Slave Hi Z input input Not selected 1 0 0 1 0 slave output input input Convert from Master to Slave 1 0 1 1 Master input output output SPCLK depends on CPOL 1 1 X 0 Slave output input input Slave 1 1 X 1 Master input output output Master http www Data...

Page 59: ...e either can be a master or a slave Master Slave 1 MISO MISO MOSI MOSI SPCLK SPCLK SS Port Pin 1 SPI single master multiple slaves configurartion Slave 2 MISO MOSI SPCLK SS Port Pin 2 Master Slave MISO MISO MOSI MOSI SPCLK SPCLK SS Port Pin SPI single master single slave configurartion http www DataSheet4U net datasheet pdf http www DataSheet4U net ...

Page 60: ... can be selected as slave device by any other master drives the idle master SS pin low Once this happened MSTR bit of the idle master is cleared by hardware and changes its state a selected slave User software should always check the MSTR bit If this bit is cleared by the mode change of SS pin and the user wants to continue to use the SPI as a master later the user must set the MSTR bit again othe...

Page 61: ...ata in software SPI slave transfer format with CPHA 1 1 2 3 4 5 6 7 8 MISO output MOSI input Driven from Master SPCLK CPOL 1 Driven from Master SPCLK CPOL 0 Driven from Master Clock Cycle SS pin if SSIG bit 0 Driven from Master DORD 0 DORD 1 DORD 0 DORD 1 MSB LSB 6 5 4 3 2 1 1 2 3 4 5 6 LSB MSB 6 5 4 3 2 1 1 2 3 4 5 6 LSB MSB MSB LSB MOSI turns to input MISO turns to output SPI slave transfer form...

Page 62: ...ORD 0 DORD 1 DORD 0 DORD 1 MSB LSB 6 5 4 3 2 1 1 2 3 4 5 6 LSB MSB 6 5 4 3 2 1 1 2 3 4 5 6 LSB MSB MSB LSB SPEN 1 and MSTR 1 MOSI turns to output data MISO turns to input data SPICLK is strongly output driving SPEN 0 or MSTR 0 MOSI switched not to output data of SPI communication also SPICLK is released from SPI control SS pin if SSIG 0 MOV SPDAT data in software http www DataSheet4U net datasheet...

Page 63: ...o register bits SPEED1 and SPEED0 Analog input source comes from P1 x one of the eight channels is multiplexed by analog multiplexer into the comparator When conversion is completed the result will be saved onto ADC_RES 7 0 ADC_RESL 1 0 register After the result has been loaded onto ADC_RES 7 0 ADC_RESL 1 0 register ADC_FLAG will be set ADC_FLAG associated with its enable register IE 5 EADC ADC_FL...

Page 64: ...k cycles 1 0 A conversion takes 420 clock cycles 1 1 A conversion takes 210 clock cycles ADC_START ADC Start control Set to start an A D conversion It will be automatically cleared by the device after the device has finished the conversion ADC_FLAG ADC Interrupt flag It will be set by the device after the device has finished a conversion and should be cleared by the user s software CHS2 CHS1 CHS0 ...

Page 65: ...00 Bit 7 6 5 4 3 2 1 0 Name The ADC_RES is the final result from the A D conversion SFR ADC_RESL Low Byte of ADC Value register Read Write Address 0XBEH Default XXXX XX00 Bit 7 6 5 4 3 2 1 0 Name The ADC_RESL Low Bytes of ADC Value register http www DataSheet4U net datasheet pdf http www DataSheet4U net ...

Page 66: ...d to slow down the system clock source in order to save power in advance Everybody knows that slower the clock oscillates less power consumed Software could program this clock divider register prior to enter the idle mode When the chip enters the idle mode the clock is switched to the divider When the chip exits the idle mode clocking will return to the original clock behavior SFR CLK_DIV Power Co...

Page 67: ...struction subsequent to the power down instruction if I O wake up is used SFR PCON Power Control Read Write Address 0X897H Default XXXX X000 Bit 7 6 5 4 3 2 1 0 Name SMOD SMOD0 LVDF POF GF1 GF0 PD IDL SMOD Double baud rate of UART interface 0 Keep normal baud rate when the UART is used in mode 1 2 or 3 1 Double baud rate when the UART is used in mode 1 2 or 3 SMOD0 SM0 FE bit select for SFR SCON 7...

Page 68: ...68 STC12C5Axx Technical Summary IDL Idle flag Set this bit to drive the device enter IDLE mode http www DataSheet4U net datasheet pdf http www DataSheet4U net ...

Page 69: ... filling the target address and data into several SFR and triggering the built in ISP automation the user can easily erase read and program the embedded flash There are several SFR designed to help the user implement the ISP functionality SFR IAP_DATA ISP Flash Data register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data to be written into flash or data got from flash IFD is the data port re...

Page 70: ...after power up moment SWRST Software Reset trigger Setting this bit will cause the device reset CFAIL ISP IAP Command Fail flag 0 The last ISP IAP command has finished successfully 1 The last ISP IAP command fails It could be caused since the access of flash memory was inhibited WAIT Waiting time selection while the flash is busy CPU Wait time Oscillator cycle IAP_CONTR 2 0 Page Erase Program Read...

Page 71: ...xxx010 B choice byte programming command IAP_CONTR 100xx010B set ISPEN 1 to enable flash change set WAIT 010 60 MC assumed 10M X s IAP_ADDRH Address high byte specify the address to be programmed IAP_ADDRL Address low byte IAP_DATA byte date to be written into flash prepare data source IAP_TRIG 5Ah trig IAP activity IAP_TRIG A5h CPU progressing will be hold here CPU continues Program a byte into f...

Page 72: ...with specific address space the hardware will ignore it Instructions Set DATA TRASFER MNEMONIC DESCRIPTION BYT CYC MOV A Rn Move register to Acc 1 1 MOV A direct Move direct byte o Acc 2 2 MOV A Ri Move indirect RAM to Acc 1 2 MOV A data Move immediate data to Acc 2 2 MOV Rn A Move Acc to register 1 2 MOV Rn direct Move direct byte to register 2 4 MOV Rn data Move immediate data to register 2 2 MO...

Page 73: ...1 2 ANL A direct AND DIRECT BYTE TO ACC 2 3 ANL A Ri AND INDIRECT RAM TO ACC 1 3 ANL A data AND IMMEDIATE DATA TO ACC 2 2 ANL direct A AND ACC TO DIRECT BYTE 2 4 ANL direct data AND IMMEDIATE DATA TO DIRECT BYTE 3 4 ORL A Rn OR REGISTER TO ACC 1 2 ORL A direct OR DIRECT BYTE TO ACC 2 3 ORL A Ri OR INDIRECT RAM TO ACC 1 3 ORL A data OR IMMEDIATE DATA TO ACC 2 2 ORL direct A OR ACC TO DIRECT BYTE 2 ...

Page 74: ...2 3 LJMP addr16 LONG JUMP 3 4 SJMP rel SHORT JUMP 2 3 JMP A DPTR JUMP INDIRECT RELATIVE TO DPTR 1 3 JZ rel JUMP IF ACC IS ZERO 2 3 JNZ rel JUMP IF ACC NOT ZERO 2 3 CJNE A direct rel COMPARE DIRECT BYTE TO ACC AND JUMP IF NOT EQUAL 3 5 CJNE A data rel COMPARE IMMEDIATE DATA TO ACC AND JUMP IF NOT EQUAL 3 4 CJNE Rn data rel COMPARE IMMEDIATE DATA TO REGISTER AND JUMP IF NOT EQUAL 3 4 CJNE Ri data re...

Page 75: ...ectional VPIN 2 4V 220 uA IIL1 Logic 0 input current Quasi bidirectional VPIN 0 45V 17 50 uA IIL2 Logic 0 input current Input Only VPIN 0 45V 0 10 uA ILK Input Leakage current Open Drain output VPIN VCC 0 10 uA IH2L Logic 1 to 0 transition current VPIN 1 8V 230 500 uA IOP Operating current FOSC 12MHz 12 30 mA IIDLE Idle mode current FOSC 12MHz 6 15 mA IPD Power down current VCC 5 0V 0 1 50 uA RRST...

Page 76: ...c 3 3V 2 8 V VIL Input Low voltage Vcc 3 3V 0 8 V IOL Output Low current VPIN 0 45V 8 14 mA IOH1 Output High current push pull VPIN 2 4V 4 8 mA IOH2 Output High current Quasi bidirectional VPIN 2 4V 64 uA IIL1 Logic 0 input current Quasi bidirectional VPIN 0 45V 7 50 uA IIL2 Logic 0 input current Input Only VPIN 0 45V 0 10 uA ILK Input Leakage current Open Drain output VPIN VCC 0 10 uA IH2L Logic ...

Page 77: ...STC12C5Axx Technical Summary 77 Package Dimension http www DataSheet4U net datasheet pdf http www DataSheet4U net ...

Page 78: ...78 STC12C5Axx Technical Summary Version History Version Date Page Description A1 2008 09 Initial issue http www DataSheet4U net datasheet pdf http www DataSheet4U net ...

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