STC12C5Axx
Technical Summary
61
Typical Timing Diagram
SPI master transfer format with CPHA=0
1
2
3
4
5
6
7
8
MOSI (Output)
MISO (Input)
Driven from the target
slave
SPCLK/CPOL=1
SPCLK/CPOL=0
Clock Cycle
Target slave SS pin
Control GPIO pin by software
DORD=0
DORD=1
DORD=0
DORD=1
MSB
LSB
6
5
4
3
2
1
1
2
3
4
5
6
LSB
MSB
6
5
4
3
2
1
1
2
3
4
5
6
LSB
MSB
MSB
LSB
SPEN=1 and MSTR=1, MOSI turns to output data
MISO turns to input data
SPICLK is strongly output-driving.
SPEN=0 or MSTR=0, MOSI switched not to output
data of SPI communication, also SPICLK is
released from SPI control
SS pin( if SSIG=0)
MOV SPDAT,#data in software
SPI slave transfer format with
CPHA=1
1
2
3
4
5
6
7
8
MISO (output)
MOSI (input)
Driven from Master
SPCLK/CPOL=1
Driven from Master
SPCLK/CPOL=0
Driven from Master
Clock
Cycle
SS pin (if SSIG bit = 0 )
Driven from Master
DORD=
0
DORD=
1
DORD=
0
DORD=
1
MSB
LSB
6
5
4
3
2
1
1
2
3
4
5
6
LSB
MSB
6
5
4
3
2
1
1
2
3
4
5
6
LSB
MSB
MSB
LSB
MOSI turns to
input
MISO turns to
output
SPI slave transfer format with CPHA=0
1
2
3
4
5
6
7
8
MISO (output)
MOSI (input)
Driven from Master
SPCLK/CPOL=1
Driven from Master
SPCLK/CPOL=0
Driven from Master
Clock Cycle
SS pin (if SSIG bit = 0 )
Driven from Master
DORD=
0
DORD=
1
DORD=
0
DORD=
1
MSB
LSB
6
5
4
3
2
1
1
2
3
4
5
6
LSB
MSB
6
5
4
3
2
1
1
2
3
4
5
6
LSB
MSB
MSB
LSB
MOSI turns to input
MISO turns to output
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datasheet pdf - http://www.DataSheet4U.net/
