STC TECHNOLOGY Co.,Ltd.
STC12C5A08/16/32/60
8-bit micro-controller
This document contains information on a new product under development by STC.STC reserves the right to change or discontinue this
product without notice. 2007/12 version A1
SFR:
CCON (PCA Counter Control Rregister)
Read/Write
Address:
0XD8FH
Default: 0XXX-X000
Bit
7
6
5
4
3
2
1
0
Name
CF CR CCF1
CCF0
CF
:= PCA Counter overflow Flag
This bit must be set by hardware itself. It can be cleared by software program.
CR
:= PCA Run control bit
0
:= (default)
Disable counting of the PCA counter
1
:=
Start counting of the PCA counter
CCF1
:= Module-1 interrupt Flag
This bit must be set by hardware itself when a match or capture from module-1 occurs.
It can be cleared by software program.
A match means the value of the PCA counter equals the value of the Capture/Compare
Register in the module-1.
A capture means a specific edge from CEX1 happens, so the Capture/Compare register
latches the value of the PCA counter, and the CCF1 is set.
CCF0
:= Module-0 interrupt Flag
This bit must be set by hardware itself when a match or capture from module-0 occurs.
It can be cleared by software program.
Each module in the PCA has a special function register associated with it,
CCAPM0
for
module0 and
CCAPM1
for module-1. The register contains the bits that control the mode in
which each module will operate. The
ECCFn
bit controls if to pass the interrupt from
CCFn
flag in the
CCON
SFR to the MCU when a match or compare occurs in the associated module.
PWMn
enables the pulse width modulation mode. The
TOGn
bit when set causes the pin
CEXn
output associated with the module to toggle when there is a match between the PCA
counter and the module’s
Capture/Compare register
. The match bit(
MATn
) when set will
cause the
CCFn
bit in the CCON register to be set when there is a match between the PCA
counter and the module’s
Capture/Compare register
.
The next two bits
CAPNn
and
CAPPn
determine the edge type that a capture input will be
active on. The
CAPNn
bit enables the negative edge, and the
CAPPn
bit enables the positive
edge. If both bits are set, both edges will be enabled and a capture will occur for either
transition. The bit
ECOMn
when set enables the comparator function.
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