Electrical characteristics
STM32F103xx
56/67
Figure 23.
ADC accuracy characteristics
Figure 24.
Typical connection diagram using the ADC
1.
Refer to
for the values of R
ADC
and C
ADC
.
2.
C
PARASITIC
must be added to C
AIN
. It represents the capacitance of the PCB (dependent on soldering and
PCB layout quality) plus the pad capacitance (3 pF). A high C
PARASITIC
value will downgrade conversion
accuracy. To remedy this, f
ADC
should be reduced.
E
O
E
G
1 LSB
IDEAL
1LSB
IDEAL
V
DDA
V
SSA
–
1024
-----------------------------------------
=
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
E
T
=Total Unadjusted Error: maximum deviation
between the actual and the ideal transfer curves.
E
O
=Offset Error: deviation between the first actual
transition and the first ideal one.
E
G
=Gain Error: deviation between the last ideal
transition and the last actual one.
E
D
=Differential Linearity Error: maximum deviation
between actual steps and the ideal one.
E
L
=Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.
1023
1022
1021
5
4
3
2
1
0
7
6
1
2
3
4
5
6
7
1021 1022 1023 1024
(1)
(2)
E
T
E
D
E
L
(3)
V
DDA
V
SSA
ai14395
ai14150
STM32F103xx
VDD
AINx
IL±1mA
0.6V
VT
RAIN
CAIN(1)
VAIN
0.6V
VT
RADC
12-bit A/D
conversion
CADC
