ST STM32F103x6, Manual

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STM32F103xx Electrical characteristics
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5.3.5 Supply current characteristics
The current consumption is measured as described in Figure 10: Current consumption
measurement scheme .
Maximum current consumption
The MCU is placed under the following conditions:
●
All I/O pins are in input mode with a static value at V
DD
or V
SS
(no load)
●
All peripherals are disabled except if it is explicitly mentioned
●
The Flash access time is adjusted to f
HCLK
frequency (0 wait state from 0 to 24 MHz, 1
wait state from 24 to 48 MHz and 2 wait states above)
The parameters given in Table 11 are derived from tests performed under ambient
temperature and V
DD
supply voltage conditions summarized in Table 7 .
Table 11. Maximum current consumption in Run and Sleep modes
(1)
Symbol Parameter Conditions F
HCLK
Typ
(2)
Max
(3)
Unit
T
A
=
85 °C
T
A
=
105 °C
I
DD
Supply
current in
Run mode
External clock with PLL, code running from
Flash, all peripherals enabled (see RCC
register description):
f
PCLK1
= f
HCLK
/2, f
PCLK2
= f
HCLK
72 MHz 36 TBD TBD
mA
48 MHz 30 TBD TBD
36 MHz 22 TBD TBD
24 MHz 21 TBD TBD
External clock, PLL stopped, code running
from Flash, all peripherals enabled (see RCC
register description):
f
PCLK1
= f
HCLK
/2, f
PCLK2
= f
HCLK
8 MHz 10 TBD TBD
External clock with PLL, code running from
RAM, all peripherals enabled (see RCC
register description):
f
PCLK1
= f
HCLK
/2, f
PCLK2
= f
HCLK
72 MHz 32 45 47
48 MHz 22 31 33
36 MHz 13 18 20
24 MHz 11 15 17
External clock, PLL stopped, code running
from RAM, all peripherals enabled (see RCC
register description):
f
PCLK1
= f
HCLK
/2, f
PCLK2
= f
HCLK
8 MHz 4.5 TBD TBD
Supply
current in
Sleep mode
External clock with PLL, code running from
RAM or Flash, all peripherals enabled (see
RCC register description):
f
PCLK1
= f
HCLK
/2, f
PCLK2
= f
HCLK
72 MHz 22 35 37
mA
48 MHz 14 23 25
36 MHz 13 22 24
24 MHz 10 17 19
External clock, PLL stopped, code running
from RAM or Flash, all peripherals enabled
(see RCC register description):
f
PCLK1
= f
HCLK
/2, f
PCLK2
= f
HCLK
8 MHz 3.5 TBD TBD
1. TBD stands for to be determined.
2. Typical values are measured at T
A
= 25 °C, and V
DD
= 3.3 V
3. Data based on characterization results, tested in production at V
Dmax
, f
HCLK
max. T
Amax,
and code executed from RAM.