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Electrical characteristics

STM32F103xx

52/67

Figure 19.

SPI timing diagram - slave mode and CPHA = 0

Measurement points are done at CMOS levels: 0.3V

and 0.7V

Figure 20.

SPI timing diagram - slave mode and CPHA = 1

ai14134

SCK Input

CPHA= 0

MOSI

I NPUT

MISO

OUT P UT

CPHA= 0

MS B O UT

M SB IN

BI T6 OUT

LSB IN

LSB OUT

CPOL=0

CPOL=1

B I T1 IN

NSS input

tSU(NSS)

tc(SCK)

th(NSS)

ta(SO)

tw(SCKH)

tw(SCKL)

tv(SO)

th(SO)

tr(SCK)

tf(SCK)

tdis(SO)

tsu(SI)

th(SI)

ai14135

SCK Input

CPHA=1

MOSI

I NPUT

MISO

OUT P UT

CPHA=1

MS B O UT

M SB IN

BI T6 OUT

LSB IN

LSB OUT

CPOL=0

CPOL=1

B I T1 IN

tSU(NSS)

tc(SCK)

th(NSS)

ta(SO)

tw(SCKH)

tw(SCKL)

tv(SO)

th(SO)

tr(SCK)

tf(SCK)

tdis(SO)

tsu(SI)

th(SI)

NSS input

Summary of Contents for STM32F103x6

Page 1: ...p registers 2 x 12 bit 1 µs A D converters 16 channel Conversion range 0 to 3 6 V Dual sample and hold capability Synchronizable with advanced control timer Temperature sensor DMA 7 channel DMA controller Peripherals supported timers ADC SPIs I2 Cs and USARTs Debug mode Serial wire debug SWD JTAG interfaces Up to 80 fast I O ports 32 49 80 5 V tolerant I Os All mappable on 16 external interrupt ve...

Page 2: ...8 64 128 SRAM Kbytes 10 20 10 20 20 Timers General purpose 2 3 2 3 3 Advanced Control 1 1 1 Communication SPI 1 2 1 2 2 I2 C 1 2 1 2 2 USART 2 3 2 3 3 USB 1 1 1 1 1 CAN 1 1 1 1 1 GPIOs 32 49 80 12 bit synchronized ADC Number of channels 2 10 channels 2 16 channels CPU frequency 72 MHz Operating voltage 2 0 to 3 6 V Operating temperature 40 to 85 C 40 to 105 C Packages LQFP48 LQFP64 LQFP100 BGA100 ...

Page 3: ...AF FLASH 128 KB VOLT REG 3 3V TO 1 8V POWER Backup interface as AF TIM 4 BusMatrix 64 bit Interface 20 KB RTC RC 8 MHz CORTEX M3 CPU Ibus Dbus pbus obl flash SRAM 512B Trace Controller USART1 USART2 SPI2 bxCAN 7 channels Backup reg 4 Channels TIM1 3 compl Channels SCL SDA SMBAL I2C1 as AF RX TX CTS RTS USART3 Temp sensor VREF PD 15 0 GPIOD PE 15 0 GPIOE AHB F max 48 72 MHz Brk input 4 Channels 4 C...

Page 4: ...A 10 PA 9 PA 8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1 VDD_3 VSS_3 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PE2 PE3 P...

Page 5: ...3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1 LQFP64 ai14392 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 48 47 46 45 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB1...

Page 6: ...D2 PC15 OSC32_OUT PB7 PB6 A 8 7 6 5 4 3 2 1 VSS_5 OSC_IN OSC_OUT VDD_5 G F E PC1 VREF PC13 ANTI_TAMP PB9 PA15 PB3 PE4 PE1 PE0 VSS_1 PD1 PE6 NRST PCD VSS_3 VSS_4 NC VDD_3 VDD_4 PB15 VBAT PD5 PD6 BOOT0 PD7 VSS_2 VSSA PA1 VDD_2 VDD_1 PB14 PA0 WKUP 10 9 K J PD10 PD11 PA8 PA9 PA10 PA11 PA12 PC10 APA13 PA14 PC9 PC7 PC6 PD15 PC8 PD14 PE12 PB1 PA7 PB11 PE8 PB0 PA6 PB10 PE13 PE9 VDDA PB13 VREF PA3 PB12 PA2...

Page 7: ... D2 11 VDD_5 S VDD_5 C1 5 5 12 OSC_IN I OSC_IN D1 6 6 13 OSC_OUT O OSC_OUT E1 7 7 14 NRST I O NRST F1 8 15 PC0 ADC_IN10 I O PC0 ADC_IN10 F2 9 16 PC1 ADC_IN11 I O PC1 ADC_IN11 E2 10 17 PC2 ADC_IN12 I O PC2 ADC_IN12 F3 11 18 PC3 ADC_IN13 I O PC3 ADC_IN13 G1 8 12 19 VSSA S VSSA H1 20 VREF S VREF J1 21 VREF S VREF K1 9 13 22 VDDA S VDDA G2 10 14 23 PA0 WKUP USART2_CTS ADC_IN0 TIM2_CH1_ETR I O PA0 WKUP...

Page 8: ... K5 40 PE9 I O FT PE9 G6 41 PE10 I O FT PE10 H6 42 PE11 I O FT PE11 J6 43 PE12 I O FT PE12 K6 44 PE13 I O FT PE13 G7 45 PE14 I O FT PE14 H7 46 PE15 I O FT PE15 J7 21 29 47 PB10 I2C2_SCL USART3_TX I O FT PB10 I2C2_SCL USART3_TX 5 6 K7 22 30 48 PB11 I2C2_SDA USART3_RX I O FT PB11 I2C2_SDA USART3_RX 5 6 E7 23 31 49 VSS_1 S VSS_1 F7 24 32 50 VDD_1 S VDD_1 K8 25 33 51 PB12 SPI2_NSS I2C2_SMBAl USART3_CK...

Page 9: ... TIM1_CH2 6 D10 31 43 69 PA10 USART1_RX TIM1_CH3 I O FT PA10 USART1_RX 6 TIM1_CH3 6 C10 32 44 70 PA11 USART1_CTS CANRX USBDM TIM1_CH4 I O FT PA11 USART1_CTS CANRX 6 TIM1_CH4 6 USBDM B10 33 45 71 PA12 USART1_RTS CANTX USBDP TIM1_ETR I O FT PA12 USART1_RTS CANTX 6 TIM1_ETR 6 USBDP A10 34 46 72 PA13 JTMS SWDIO I O FT JTMS SWDIO PA13 F8 73 Not connected E6 35 47 74 VSS_2 S VSS_2 F6 36 48 75 VDD_2 S VD...

Page 10: ... Function availability depends on the chosen device Refer to Table 2 on page 7 4 PC13 PC14 and PC15 are supplied through the power switch and so their use in ouptut mode is limited they can be used only in output 2 MHz mode with a maximum load of 30 pF and only one pin can be put in output mode at a time 5 Available only on devices with a Flash memory density equal or higher than 64 Kbytes 6 This ...

Page 11: ...bit 2 Kbits 1 Kbit 1 Kbit 2 Kbits 1 Kbit 1 Kbit 1 Kbit 1 Kbit 1 Kbit 7 Kbits 1 Kbit Port E PWR Port B 1 Kbit 1 Kbit 1 Kbit 3 Kbits 1 Kbit 1 Kbit 1 Kbit 1 Kbit 1 Kbit 1 Kbit 1 Kbit 1 Kbit 2 Kbits 1 Kbit 1 Kbit 1 Kbit I2C2 reserved bxCAN EXTI reserved RCC reserved Flash Interface reserved reserved reserved 0x4000 6400 0x4000 6800 0x4000 6C00 0x4000 7000 0x4000 7400 0x4001 0000 0x4001 0400 0x4002 200...

Page 12: ...4141 C 50 pF STM32F103xx pin ai14142 STM32F103xx pin VIN ai14125 3 3V VDD 1 2 3 4 5 Analog RCs PLL Power switch VBAT 3 3 V GP I Os OUT IN Kernel logic CPU Digital Memories Backup circuitry OSC32K RTC Backup registers Wake up logic 5 100 nF 1 10 µF 1 8 3 6 V Regulator VSS 1 2 3 4 5 VDDA VREF VREF VSSA ADC Level shifter IO Logic VDD 10 nF 1 µF VREF 10 nF 1 µF VDD ...

Page 13: ...STM32F103xx Electrical characteristics 25 67 5 1 7 Current consumption measurement Figure 10 Current consumption measurement scheme ai14126 VBAT VDD VDDA IDD_VBAT IDD ...

Page 14: ...nt ground pins 50 50 VESD HBM Electrostatic discharge voltage human body model see Section 5 3 11 Absolute maximum ratings electrical sensitivity Table 5 Current characteristics Symbol Ratings Max Unit IVDD Total current into VDD power lines source 1 1 All 3 3 V power VDD VDDA and ground VSS VSSA pins must always be connected to the external 3 3 V supply 150 mA IVSS Total current out of VSS ground...

Page 15: ...racteristics Symbol Ratings Value Unit TSTG Storage temperature range 65 to 150 C TJ Maximum junction temperature see Thermal characteristics Table 7 General operating conditions Symbol Parameter Conditions Min Max Unit fHCLK Internal AHB clock frequency 0 72 MHz fPCLK1 Internal APB1 clock frequency 0 36 fPCLK2 Internal APB2 clock frequency 0 72 VDD Standard operating voltage 2 3 6 V VBAT Backup o...

Page 16: ... 0 001 falling edge 2 09 2 18 2 27 V PLS 2 0 010 rising edge 2 28 2 38 2 48 V PLS 2 0 010 falling edge 2 18 2 28 2 38 V PLS 2 0 011 rising edge 2 38 2 48 2 58 V PLS 2 0 011 falling edge 2 28 2 38 2 48 V PLS 2 0 100 rising edge 2 47 2 58 2 69 V PLS 2 0 100 falling edge 2 37 2 48 2 59 V PLS 2 0 101 rising edge 2 57 2 68 2 79 V PLS 2 0 101 falling edge 2 47 2 58 2 69 V PLS 2 0 110 rising edge 2 66 2 ...

Page 17: ...CLK2 fHCLK 72 MHz 36 TBD TBD mA 48 MHz 30 TBD TBD 36 MHz 22 TBD TBD 24 MHz 21 TBD TBD External clock PLL stopped code running from Flash all peripherals enabled see RCC register description fPCLK1 fHCLK 2 fPCLK2 fHCLK 8 MHz 10 TBD TBD External clock with PLL code running from RAM all peripherals enabled see RCC register description fPCLK1 fHCLK 2 fPCLK2 fHCLK 72 MHz 32 45 47 48 MHz 22 31 33 36 MHz...

Page 18: ...g TBD 4 14 4 TBD 4 TBD 4 Supply current in Standby mode 5 Low speed internal RC oscillator and independent watchdog OFF low speed oscillator and RTC OFF TBD 4 2 4 TBD 4 TBD 4 IDD_VBAT Backup domain supply current Low speed oscillator and RTC ON 1 4 1 4 4 TBD 4 TBD 4 1 TBD stands for to be determined 2 Typical values are measured at TA 25 C VDD 3 3 V unless otherwise specified 3 Data based on chara...

Page 19: ...ption fPCLK1 fHCLK 2 fPCLK2 fHCLK 72 MHz 21 mA 48 MHz 18 36 MHz TBD 24 MHz 13 16 MHz TBD Running on HSI clock code running from Flash all peripheral disabled see RCC register description fPCLK1 fHCLK 2 fPCLK2 fHCLK AHB pre scaler used to reduce the frequency 8 MHz 7 8 mA 4 MHz 7 2 MHz 6 3 1 MHz 6 2 500 kHz 6 1 125 kHz 5 95 Running on HSI clock code running from RAM all peripheral disabled see RCC ...

Page 20: ... TBD 3 Supply current in Standby mode 4 Low speed internal RC oscillator and independent watchdog OFF 3 3 V 2 3 µA 2 4 V TBD 3 Low speed internal RC oscillator and independent watchdog ON 3 3 V 3 1 3 2 4 V TBD 3 Low speed internal RC oscillator ON independent watchdog OFF 3 3 V 2 9 3 2 4 V TBD 3 IDD_VBAT Backup domain supply current Low speed oscillator and RTC ON 3 3 V 1 4 3 µA 2 4 V 1 3 Low spee...

Page 21: ...cy 1 1 Value based on design simulation and or technology characteristics It is not tested in production 8 25 MHz VHSEH OSC_IN input pin high level voltage 0 7VDD VDD V VHSEL OSC_IN input pin low level voltage VSS 0 3VDD tw HSE tw HSE OSC_IN high or low time 1 16 ns tr HSE tf HSE OSC_IN rise or fall time 1 5 IL OSC_IN Input leakage current VSS VIN VDD 1 µA Table 16 Low speed external user clock ch...

Page 22: ... diagram Figure 12 Low speed external clock source AC timing diagram ai14143 OSC_IN EXTERNAL STM32F103xx CLOCK SOURCE VHSEH tf HSE tW HSE IL 90 10 THSE t tr HSE tW HSE fHSE_ext VHSEL ai14144b OSC32_IN EXTERNAL STM32F103xx CLOCK SOURCE VLSEH tf LSE tW LSE IL 90 10 TLSE t tr LSE tW LSE fLSE_ext VLSEL ...

Page 23: ...ge typ designed for high frequency applications and selected to match the requirements of the crystal or resonator CL1 and CL2 are usually the same size The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2 PCB and MCU pin capacitance must be included when sizing CL1 and CL2 10 pF can be used as a rough estimate of the combined pin and board...

Page 24: ...cteristics fLSE 32 768 kHz Symbol Parameter Conditions Min Typ Max Unit RF Feedback resistor 5 MΩ CL1 CL2 Recommended load capacitance versus equivalent serial resistance of the crystal RS 1 1 The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value for example MSIV TIN32 768kHz Refer to crystal manufacturer for more details RS 30 kΩ ...

Page 25: ...ned Symbol Parameter Conditions Min Typ Max 3 3 Values based on device characterization not tested in production Unit fHSI Frequency 8 MHz ACCHSI Accuracy of HSI oscillator TA 40 to 105 C TBD 3 TBD at TA 25 C TBD 1 TBD tsu HSI HSI oscillator start up time 1 2 µs IDD HSI HSI oscillator power consumption 80 100 µA Table 20 LSI oscillator characteristics 1 1 VDD 3 V TA 40 to 105 C unless otherwise sp...

Page 26: ...e are measured from the wakeup event to the point in which the user application code reads the first instruction Wakeup from Sleep mode Wakeup on HSI RC clock 0 75 TBD µs tWUSTOP 2 Wakeup from Stop mode regulator in run mode HSI RC wakeup time 2 µs 4 TBD µs Wakeup from Stop mode regulator in low power mode HSI RC wakeup time 2 µs Regulator wakeup from LP mode time 5 µs 7 TBD tWUSTDBY 3 3 The wakeu...

Page 27: ...n and not tested in production Unit tprog Word programming time TA 40 to 105 C 20 40 µs tERASE Page 1kB erase time TA 40 to 105 C 20 40 ms tME Mass erase time TA 40 to 105 C 20 40 ms IDD Supply current Read mode fHCLK 72 MHz with 2 wait states VDD 3 3 V 20 mA Write Erase modes fHCLK 72 MHz VDD 3 3 V 5 mA Power down mode HALT VDD 3 0 to 3 6 V 50 µA Symbol Parameter Conditions Value Unit Min 1 1 Val...

Page 28: ...in application note AN1709 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software It should be noted that good EMC performance is highly dependent on the user application and the software in particular Therefore it is recommended that the user applies EMC software ...

Page 29: ...event unrecoverable errors occurring see application note AN1015 Electromagnetic Interference EMI The electromagnetic field emitted by the device are monitored while a simple application is executed toggling 2 LEDs through the I O ports This emission test is compliant with SAE J 1752 3 standard which specifies the test board and the pin loading Table 26 EMI characteristics Symbol Parameter Conditi...

Page 30: ...ESD22 A114A standard For more details refer to the application note AN1181 Static latch up Two complementary static tests are required on six parts to assess the latch up performance A supply overvoltage is applied to each power supply pin A current injection is applied to each input output and configurable I O pin These tests are compliant with EIA JESD 78A IC latch up standard Table 27 ESD absol...

Page 31: ...level voltage 2 2 VDD 0 5 IO FT high level voltage 2 2 5 5V VIL Input low level voltage 2 CMOS ports 0 5 0 35 VDD V VIH Input high level voltage 2 0 65 VDD VDD 0 5 Vhys IO TC Schmitt trigger voltage hysteresis 3 3 Hysteresis voltage between Schmitt trigger switching levels Based on characterization results not tested 200 mV IO TC Schmitt trigger voltage hysteresis 3 5 VDD 4 4 With a minimum of 100...

Page 32: ...mited to respect the absolute maximum rating specified in Section 5 2 The sum of the currents sourced by all the I Os on VDD plus the maximum Run consumption of the MCU sourced on VDD cannot exceed the absolute maximum rating IVDD see Table 5 The sum of the currents sunk by all the I Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS se...

Page 33: ... by the device must always respect the absolute maximum rating specified in Table 5 and the sum of IIO I O ports and control pins must not exceed IVDD Output high level voltage for an I O pin when 4 pins are sourced at same time VDD 0 4 VOL 1 Output low level voltage for an I O pin when 8 pins are sunk at same time CMOS port IIO 8mA 2 7 V VDD 3 6 V 0 4 V VOH 2 Output high level voltage for an I O ...

Page 34: ... to low level fall time 3 3 Values based on design simulation and validated on silicon not tested in production CL 50 pF VDD 2 V to 3 6 V 125 ns tr IO out Output low to high level rise time 3 125 01 fmax IO out Maximum frequency 2 CL 50 pF VDD 2 V to 3 6 V 10 MHz tf IO out Output high to low level fall time 3 CL 50 pF VDD 2 V to 3 6 V 25 ns tr IO out Output low to high level rise time 3 25 11 Fmax...

Page 35: ...3 T and if the duty cycle is 45 55 10 50 90 when loaded by 50pF T tr IO out Table 32 NRST pin characteristics 1 1 TBD stands for to be determined Symbol Parameter Conditions Min Typ Max Unit VIL NRST NRST Input low level voltage 0 5 0 8 V VIH NRST NRST Input high level voltage 2 VDD 0 5 Vhys NRST NRST Schmitt trigger voltage hysteresis 200 RPU Weak pull up equivalent resistor 2 2 The pull up is de...

Page 36: ... 12 I O port pin characteristics for details on the input output alternate function characteristics output compare input capture external clock PWM output ai14132b STM32F101xx RPU NRST VDD FILTER Internal Reset 0 1 µF External reset circuit Table 33 TIMx 1 characteristics 1 TIMx is used as a general term to refer to the TIM1 TIM2 TIM3 and TIM4 timers Symbol Parameter Conditions Min Max Unit tres T...

Page 37: ...cteristics for more details on the input output alternate function characteristics SDA and SCL Table 34 I2C characteristics Symbol Parameter Standard mode I2 C 1 1 Values based on standard I2 C protocol requirement not tested in production Fast mode I2 C 1 2 2 fPCLK1 must be higher than 2 MHz to achieve the maximum standard mode I2C frequency It must be higher than 4 MHz to achieve the maximum fas...

Page 38: ...ds around 200 kHz the tolerance on the achieved speed is of 5 For other speed ranges the tolerance on the achieved speed 2 These variations depend on the accuracy of the external components used to design the application fSCL kHz I2C_CCR value RP 4 7 kΩ 400 TBD 300 TBD 200 TBD 100 TBD 50 TBD 20 TBD ai14149b START SDA 100Ω 4 7kΩ I2C bus 4 7kΩ 100Ω VDD VDD STM32F103xx SDA SCL tf SDA tr SDA SCL th ST...

Page 39: ... mode 0 tw SCKH 2 tw SCKL 2 SCK high and low time Master mode fPCLK TBD presc TBD TBD tsu MI 2 tsu SI 2 Data input setup time Master mode TBD Slave mode TBD th MI 2 th SI 2 Data input hold time Master mode TBD Slave mode TBD Master mode fPCLK TBD TBD 3 3 Depends on fPCLK For example if fPCLK 8MHz then tPCLK 1 fPLCLK 125 ns and tv MO 255 ns Slave mode fPCLK TBD TBD 3 ta SO 2 4 4 Min time is for the...

Page 40: ...nput CPHA 0 MOSI INPUT MISO OUT PUT CPHA 0 MSB O UT M SB IN BIT6 OUT LSB IN LSB OUT CPOL 0 CPOL 1 BIT1 IN NSS input tSU NSS tc SCK th NSS ta SO tw SCKH tw SCKL tv SO th SO tr SCK tf SCK tdis SO tsu SI th SI ai14135 SCK Input CPHA 1 MOSI INPUT MISO OUT PUT CPHA 1 MSB O UT M SB IN BIT6 OUT LSB IN LSB OUT CPOL 0 CPOL 1 BIT1 IN tSU NSS tc SCK th NSS ta SO tw SCKH tw SCKL tv SO th SO tr SCK tf SCK tdis...

Page 41: ...ut levels VDI Differential input sensitivity I USBDP USBDM 0 2 V VCM Differential common mode range Includes VDI range 0 8 2 5 VSE Single ended receiver threshold 1 3 2 0 Output levels VOL Static output level low RL of 1 5 kΩto 3 6 V 2 2 RL is the load connected on the USB drivers 0 3 V VOH Static output level high RL of 15 kΩto VSS 2 2 8 3 6 ai14136 SCK Input CPHA 0 MOSI OUTUT MISO INPUT CPHA 0 M...

Page 42: ... USB Full speed electrical characteristics Symbol Parameter Conditions Min Max Unit Driver characteristics tr Rise time 1 1 Measured from 10 to 90 of the data signal For more detailed informations please refer to USB Specification Chapter 7 version 2 0 CL 50 pF 4 20 ns tf Fall Time 1 CL 50 pF 4 20 ns trfm Rise fall time matching tr tf 90 110 VCRS Output signal crossover voltage 1 3 2 0 V ai14137 t...

Page 43: ...internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS After the end of the sample time tS changes of the analog input voltage have no effect on the conversion result Values for the sample clock tS depend on programming Table 40 ADC accuracy fPCLK2 14 MHz fADC 14 MHz RAIN 10 kΩ VDDA 3 3 V 1 1 TBD to be determined Symbol Parameter Conditions T...

Page 44: ...ve 2 The ideal transfer curve 3 End point correlation line ET Total Unadjusted Error maximum deviation between the actual and the ideal transfer curves EO Offset Error deviation between the first actual transition and the first ideal one EG Gain Error deviation between the last ideal transition and the last actual one ED Differential Linearity Error maximum deviation between actual steps and the i...

Page 45: ...be placed them as close as possible to the chip Figure 25 Power supply and reference decoupling VREF not connected to VDDA 1 VREF and VREF inputs are available only on 100 pin packages Figure 26 Power supply and reference decoupling VREF connected to VDDA 1 VREF and VREF inputs are available only on 100 pin packages VREF see note 1 STM32F103xx VDDA VSSA VREF see note 1 1 µF 10 nF 1 µF 10 nF ai1438...

Page 46: ...5 3 18 Temperature sensor characteristics Table 41 TS characteristics Symbol Parameter Conditions Min Typ Max Unit TL VSENSE linearity with temperature 1 5 C Avg_Slope Average slope 4 478 mV C V25 Voltage at 25 C 1 4 V tSTART Startup time 4 10 µs ...

Page 47: ...067 A1 0 270 0 011 A2 1 085 0 043 A3 0 30 0 012 A4 0 80 0 031 b 0 45 0 50 0 55 0 018 0 020 0 022 D 9 85 10 00 10 15 0 388 0 394 0 40 D1 7 20 0 283 E 9 85 10 00 10 15 0 388 0 394 0 40 E1 7 20 0 283 e 0 80 0 031 F 1 40 0 055 ddd 0 12 0 005 eee 0 15 0 006 fff 0 08 0 003 N number of balls 100 ai14396 A2 A4 A3 A1 A Seating plane B A1 corner index area see note 5 100 balls Bottom view 1 2 3 4 5 6 7 8 9 ...

Page 48: ...e 28 Recommended PCB design rules 0 80 0 75 mm pitch BGA Dpad Dsm Dpad 0 37 mm Dsm 0 52 mm typ depends on solder mask registration tolerance Solder paste 0 37 mm aperture diameter Non solder mask defined pads are recommended 4 to 6 mils screen print ...

Page 49: ...data Dim mm inches Min Typ Max Min Typ Max A 1 60 0 063 A1 0 05 0 15 0 002 0 006 A2 1 35 1 40 1 45 0 053 0 055 0 057 b 0 17 0 22 0 27 0 007 0 009 0 011 C 0 09 0 20 0 004 0 008 D 16 00 0 630 D1 14 00 0 551 E 16 00 0 630 E1 14 00 0 551 e 0 50 0 020 θ 0 3 5 7 0 3 5 7 L 0 45 0 60 0 75 0 018 0 024 0 030 L1 1 00 0 039 Number of pins N 100 h c L L1 e b A A2 A1 D D1 E E1 ai14397 ...

Page 50: ...data Dim mm inches Min Typ Max Min Typ Max A 1 60 0 063 A1 0 05 0 15 0 002 0 006 A2 1 35 1 40 1 45 0 053 0 055 0 057 b 0 17 0 22 0 27 0 007 0 009 0 011 c 0 09 0 20 0 004 0 008 D 12 00 0 472 D1 10 00 0 394 E 12 00 0 472 E1 10 00 0 394 e 0 50 0 020 θ 0 3 5 7 0 3 5 7 L 0 45 0 60 0 75 0 018 0 024 0 030 L1 1 00 0 039 Number of pins N 64 A A2 A1 c L1 L E E1 D D1 e b ai14398 ...

Page 51: ...hes are converted from mm and rounded to 3 decimal digits Min Typ Max Min Typ Max A 1 60 0 063 A1 0 05 0 15 0 002 0 006 A2 1 35 1 40 1 45 0 053 0 055 0 057 b 0 17 0 22 0 27 0 007 0 009 0 011 C 0 09 0 20 0 004 0 008 D 9 00 0 354 D1 7 00 0 276 E 9 00 0 354 E1 7 00 0 276 e 0 50 0 020 θ 0 3 5 7 0 3 5 7 L 0 45 0 60 0 75 0 018 0 024 0 030 L1 1 00 0 039 Number of pins N 48 E E1 D D1 L1 L c e b A1 A2 A ai...

Page 52: ...igured to drive continuously external modules and or memories An approximate relationship between PD and TJ if PI O is neglected is given by PD K TJ 273 C 2 Therefore solving equations 1 and 2 K PD x TA 273 C ΘJA x PD 2 3 where K is a constant for the particular part which may be determined from equation 3 by measuring PD at equilibrium for a known TA Using this value of K the values of PD and TJ ...

Page 53: ...up to 512KB Flash 64KB SRAM and with extended features such as EMI support SDIO I2S DAC and additional timers and USARTS Table 47 Order codes Part number Flash program memory Kbytes SRAM memory Kbytes Package STM32F103C6T6 32 10 LQFP48 STM32F103C8T6 64 20 STM32F103R6T6 32 10 LQFP64 STM32F103R8T6 64 20 STM32F103RBT6 128 20 STM32F103V8T6 64 20 LQFP100 STM32F103VBT6 128 20 STM32F103V8H6 64 20 LFBGA10...

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