Sony NSS-S2, Installation Manual

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2-3 (E)
NSS-S2
Ref. No. Address Name Function Factory setting
S1503 (A-2) CPU_FPGA_RECONF Reconfigures CPU_FPGA (IC1601). _
S2001 (F-9) Reset switch Initializes the PU-124 board. _
S2002 (E-1) BATT Turn the SRAM data backup battery ON/OFF. ON
ON : For normal use
OFF : For production
S2003 (F-1) HOT PLAG CONTROL For debug “2” side
“2” side (the side without ) : For normal use
S2005 (E-3) DD-CON CONTROL S2005-1 ON : 12 V
→
5 V (generic) DD converter All OFF
Standby connect from ISPPAC
S2005-2 ON : 12 V
→
3.3 V (generic) DD converter
Standby connect from ISPPAC
S2005-3 ON : 3.3 V
→
2.5 V (DDR-DRAM)
DD converter Standby connect from
ISPPAC
S2005-4 ON : 3.3 V
→
1.5 V (FPGA core)
LDO Standby connect from ISPPAC
S2502 (J-8) APL setting switch For soft-debug (do not change except for factory All OFF
setting)
S2502-1 to 8 all OFF : For normal use
S4001 (G-9) IFPLD setting switch S4001-1 ON : JTAG CPU (CPU FLASH ACSESS)
S4001-2 ON : DW MODE
S4001-3 ON : M MODE
S4001-4 ON : MODE
S4001-5 :
Not used
S4001-6 : Not used
S4001-7 ON : XWP_ACC
S4001-8 ON : IFPLD1_SEL
S4002 (F-9) ISP selection switch S4002-1 ON : ALTERA LOOP 1 * 1 enable
S4002-2 ON : ALTERA LOOP 2 * 2 enable
S4002-3 ON : LATTICE LOOP * 3 enable
S4002-4 ON : IFPLD LOOP * 4 enable
S4002-5 ON : RS-232C
(using Max Driver IC (using CN2501))
S4002-6 to 8 : Not used
Turn on only one of the bits from S4002-1 to 4.
(Do not turn on two or more bits.)
* 1 : JTAG : IFPLD1
→
IFPLD2
→
MPU_PLD (when connected to the MPU-136 board)
* 2 : JTAG : CFPGA
* 3 : JTAG : ISPPAC
* 4 : JTAG : RAID_FPGA (using download tool)
S4501 (E-7) FPGA (IC4501) For hard-debug (do not change except for factory All OFF
setting switch setting)
S4501-1 to 8 all OFF : For normal use
ON
1 2 3 4
ON
1 2 3 4 5 6 7 8
ON
1 2 3 4 5 6 7 8
ON
1
2 3 4 5 6 7 8
ON
1 2 3 4 5 6 7 8