Sony DXC-S500, Service Manual

Page: 64 / 148

7-10
DXC-S500 (E)
MD8408B (FMD)
IEEE 1394 PHYSICAL LAYER CONTROLLER
—TOP VIEW—
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
I
—
O
—
I/O
I/O
—
I/O
I/O
I/O
I/O
—
I/O
I/O
I/O
I/O
LREQ
D.V
CC
SCLK
D.GND
CTL0
CTL1
D.V
CC
D0
D1
D2
D3
D.GND
D4
D5
D6
D7
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
—
—
I
I
—
—
-—
I
—
—
—
—
I/O
I/O
—
—
D.V
CC
D.V
CC
TEST0
TEST1
D.GND
D.V
CC
D.GND
PURB
A.GND
NC
NC
A.V
CC
1
XEXT
XTAL
AGND
A.V
CC
1
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
I
—
—
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
—
—
CPS
A.GND
A.V
CC
1
TPBIAS1
TPBIAS0
TPB1N
TPB1P
TPA1N
TPA1P
TPB0N
TPB0P
TPA0N
TPA0P
A.GND
A.V
CC
2
D.GND
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
I
I
I
I
—
I
I
I
I
—
O
I
I
I
I
I
DISABLED1
DISABLED0
S200
LDSEL
D.V
CC
EN ACCEL
EN MULTI
SR
DIRECT
D.GND
LINKON
PC2
PC1
PC0
CMC
LPS
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16
INPUTS
CMC
CPS
DIRECT
DISABLED0, DISABLED1
EN ACCEL
EN MULTI
LDSEL
LPS
LREQ
PC0 - PC2
PURB
S200
SR
TEST0, TEST1
OUTPUTS
LINKON
SCLK
TPBIAS0, TPBIAS1
INPUTS/OUTPUTS
CTL0, CTL1
D0 - D7
TPA0N, TPA1N,
TPA0P, TPA1P
TPB0N, TPB1N,
TPB0P, TPB1P
XEXT, XTAL
: CONFIGURATION MANAGEMENT CAPABLE
: CABLE POWER STATUS
: PHY-LINK INTERFACE OPERATION MODE SETTING
: HARDWARE RESET DEFAULT OF DISABLED BIT
: HARDWARE RESET DEFAULT OF EN ACCEL BIT
: HARDWARE RESET DEFAULT OF EN MULT BIT
: PHY-LINK INTERFACE TIMING
: LINK POWER STATUS
: LINK REQUEST
: POWER CLASS
: EXTERNAL CAPACITOR FOR POWER UP RESET
: SPEED CHANGE
: SUSPEND/RESUME
: TEST
: LINK ON
: SYSTEM CLOCK
: CABLE BIAS
: PHY-LINK INTERFACE CONTROL
: PHY-LINK INTERFACE DATA
: ARBITRATION/STROBE OUTPUT,
ARBITRATION/SPEED SIGNAL/DATA INPUT
: ARBITRATION/SPEED SIGNAL/DATA OUTPUT,
ARBITRATION/STROBE INPUT
: OSCILLATOR
CPS
33
TPBIAS1
TPBIAS0
36
37
TPA0N
TPA0P
TPB0N
TPB0P
44
45
42
43
LDSEL
LPS
DIRECT
52
64
57
TEST0, TEST1
19, 20
SCLK
LREQ
3
1
CTL0, CTL1
5,6
D0 - D7
8 - 11,
13 - 16
PURB
24
PC0 - PC2
60 - 62
CMC
63
LINKON
59
EN ACCEL
54
EN MULTI
55
DISABLED0,
DISABLED1
49, 50
CABLE
POWER
STATUS
TPBIAS GEN.
LINK
INTERFACE
DS-LINK
ENCODER/DECODER
VOLTAGE -
CURRENT
GEN.
XEXT
XTAL
29
30
393.216 MHz CLK
24.576 MHz
CRYSTAL
OSCILLATOR
PLL
TRANSMITTER
&
RECEIVER
TPA1N
TPA1P
TPB1N
TPB1P
40
41
38
39
TRANSMITTER
&
RECEIVER
CONTROL
UNIT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
INPUTS
A0 - A18
CE1
,
CE2
LB
,
UB
OE
WE
INPUTS/OUTPUTS
I/O1 - I/O16
OTHER
NC
: ADRRESS
: CHIP ENABLE
: BYTE DATA SELECT
: OUTPUT ENABLE
: WRITE ENABLE
: DATA
: NO CONNECTION
1
2
3
4
5
6
7
8
9
10
11
12
I
I
I
I
I
I
I
I
—
—
I
I
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
CE2
13
14
15
16
17
18
19
20
21
22
23
24
—
I
I
I
I
I
I
I
I
I
I
I
NC
UB
LB
A18
A17
A7
A6
A5
A4
A3
A2
A1
25
26
27
28
29
30
31
32
33
34
35
36
I
I
—
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A0
CE1
GND
OE
I/O1
I/O9
I/O2
I/O10
I/O3
I/O11
I/O4
I/O12
37
38
39
40
41
42
43
44
45
46
47
48
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
—
I
V
CC
I/O5
I/O13
I/O6
I/O14
I/O7
I/O15
I/O8
I/O16
GND
NC
A16
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
PIN
NO.
I/O SIGNAL
8M (524288 x 16) - BIT SRAM
—TOP VIEW—
UPD448012GY-B70X-MJH (NEC)
IC