Chapter 15
E300 Pulse-Width Modulation (PWM)
Peripheral
This chapter describes the operation of the E300 Pulse-Width Modulation peripheral (PWM).
PWM Overview
Figure 15.1 shows an overview of the PWM peripheral. The default configuration described here
has four independent PWM comparators (
pwmcmp0
–
pwmcmp3
), but custom configurations with
ncmp
comparators are available on request. The PWM block can generate multiple types of waveform
on GPIO output pins (
pwm
X
gpio
), and can also be used to generate several forms of internal timer
interrupt. The comparator results are captured in the
pwmcmp
X
ip
flops and then fed to the PLIC as
potential interrupt sources. The
pwmcmp
X
ip
outputs are further processed by an output ganging
stage before being fed to the GPIOs.
The PWM unit can be provided in different comparator precisions up to 16 bits, with the version
described here having the full 16 bits. To support clock scaling, the
pwmcount
register is 15 bits
wider than the comparator precision,
cmpwidth
.
PWM Memory Map
The memory map for the PWM peripheral is shown in Table 15.1.
PWM Count Register (
pwmcount
)
The PWM unit is based around a counter held in
pwmcount
. The counter can be read or written
over the TileLink bus. The
pwmcount
register is
(15 +
cmpwidth
)
bits wide. For example, for
cmpwidth
of 16 bits, the counter is held in
pwmcount[30:0]
, and bit 31 of
pwmcount
returns a zero
when read.
When used for PWM generation, the counter is normally incremented at a fixed rate then reset to
zero at the end of every PWM cycle. The PWM counter is either reset when the scaled counter
pwms
reaches the value in
pwmcmp0
, or is simply allowed to wraparound to zero.
The counter can also be used in one-shot mode, where it disables counting after the first reset.
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