28
SiFive E300 Platform Reference Manual, Version 1.0.1
Watchdog Interrupts (
wdogcmpip
)
The WDT can be configured to provide periodic counter interrupts by disabling watchdog re-
sets (
wdogrsten
=0) and enabling auto-zeroing of the count register when the comparator fires
(
wdogzerocmp
=1).
The sticky single-bit
wdogcmpip
register captures the comparator output and holds it to provide an
interrupt pending signal. The
wdogcmpip
register resides in bit 28 of the
wdogcfg
register, and can
be read and written over TileLink to clear down the interrupt.
Summary of Contents for E300
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