SiFive E300, Reference Manual

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Chapter 13
Serial Peripheral Interface (SPI)
This chapter describes the operation of the SiFive Serial Peripheral Interface (SPI) controller.
SPI Overview
The SPI controller supports master-only operation over the single-lane, dual-lane, and quad-lane
protocols. The baseline controller provides a FIFO-based interface for performing programmed
I/O. Software initiates a transfer by enqueuing a frame in the transmit FIFO; when the transfer
completes, the slave response is placed in the receive FIFO.
In addition, the dedicated SPI0 controller implements a SPI flash read sequencer, which exposes
the external SPI flash contents as a read/execute-only memory-mapped device. The SPI0 con-
troller is reset to a state which allows memory-mapped reads, under the assumption that the input
clock rate is less than 100 MHz and the external SPI flash device supports the common Win-
bond/Numonyx serial read (
0x03
) command. Sequential accesses are automatically combined
into one long read command for higher performance.
The
fctrl
register controls switching between the memory-mapped and programmed-I/O modes.
While in programmed-I/O mode, memory-mapped reads do not access the external SPI flash
device and instead return
0
immediately. Hardware interlocks ensure that the current transfer
completes before mode transitions and control register updates take effect.
Memory Map
The memory map for the SPI control registers is shown in Table 13.1. The SPI memory map has
been designed to only require naturally aligned 32-bit memory accesses.
Serial Clock Divisor Register (
sckdiv
)
The
sckdiv
register specifies the divisor used for generating the serial clock (SCK). The relation-
ship between the input clock and SCK is given by the following formula:
f
sck
=
f
in
2( div + 1)
The input clock is the bus clock
tlclk
. The reset value of the
div
field is 0x003.
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