SiFive E300, Reference Manual

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c
2016, SiFive Inc. All rights reserved. 51
Programmed-I/O Sequencing
The programmed-I/O interface exposes the OTP device’s and power-supply’s control signals di-
rectly to software. Software is responsible for respecting these signals’ setup and hold times.
The OTP device requires that data be programmed one bit at a time and that the result be re-read
and retried according to a specific protocol.
See the OTP device and power supply data sheets for timing constraints, control signal descrip-
tions, and the programming algorithm.
Read sequencer control register (
otp rsctrl
)
The read sequence consists of an address-setup phase, a read-pulse phase, and a read-access
phase. The duration of these phases, in terms of controller clock cycles, is set by a programmable
clock divider. The divider is controlled by the
otp rsctrl
register, the layout of which is shown in
Figure 14.2
The number of clock cycles in each phase is given by 2
scale
, and the width of each phase may be
optionally scaled by 3. That is, the number of controller clock cycles in the address-setup phase
is given by the expression
2
scale
(1 + 2 t
AS
) ; the number of clock cycles in the read-pulse phase is
given by 2
scale
(1 + 2 t
RP
) ; and the read-access phase is 2
scale
(1 + 2 t
RACC
) cycles long. The reset
value of
scale
is 1.
Software should acquire the
otp lock
prior to modifying
otp rsctrl
.
R
es
er
ve
d
31 6
t
RACC
5
t
RP
4
t
AS
3
scale
2 0
Figure 14.2: Read sequencer control register
otp rsctrl