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Advanced Chipset Features
Dram Timing By SPD
This item allows you to enable or disable the DRAM timing defined by
the Serial Presence Detect electrical.
Ø
The choice: Enabled, Disabled.
SDRAM Cycle Length
This field enables you to set the CAS latency time in HCLKs of 2/2 or 3/
3. The system board designer should have set the values in this field,
depending on the DRAM installed. Do not change the values in this
field unless you change specifications of the installed DRAM or the
installed CPU.
Ø
The choice: 2, 3.
Bank Interleave
This item allows you to enable or disable the Bank Interleave function
with 2 banks or 4 banks.
Ø
The choice: Disabled, 2 Bank, or 4 Bank.
System BIOS Cacheable
When this is enabled, system BIOS will be cached for faster execution.
Ø
The choice: Enabled, Disabled.
