PC-UM10M
SL-5500 HARDWARE DESCRIPTION
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nPIOW
OCZ
PCMCIA I/O write. This signal is an output and is used to perform write transactions to the PCMCIA I/O
space.
nPIOR
OCZ
PCMCIA I/O read. This signal is an output and is used to perform read transactions from the PCMCIA I/O
space.
nPCE 2:1
OCZ
PCMCIA card enable. These signals are output and are used to select a PCMCIA card. nPCE 2 enables
the high-byte lane and nPCE 1 enables the low-byte lane.
nIOIS16
IC
I/O Select 16. This signal is an input and is an acknowledgment from the PCMCIA card that it can perform
16-bit I/O data transfers.
nPWAIT
IC
PCMCIA wait. This signal is an input and is driven low by the PCMCIA card to extend the duration of
transfers to/from the SA-1110.
PSKTSEL
OCZ
PCMCIA socket select. This signal is an output and used by external steering logic to route control,
address, and data signals to one of the PCMCIA sockets. When PSKTSEL is low, socket zero is selected.
When PSKTSEL is high, socket one is selected. This signal has the same timing as the address lines.
nPREG
OCZ
PCMCIA register select. This signal is an output and indicates that, on a memory transaction, the target
address is attribute space. This signal has the same timing as address.
L_DD 7:0
OCZ
LCD controller display data.
L_FCLK
OCZ
LCD frame clock.
L_LCLK
OCZ
LCD line clock.
L_PCLK
OCZ
LCD pixel clock.
L_BIAS
OCZ
LCD ac bias drive.
TXD_C
OCZ
CODEC transmit.
RXD_C
IC
CODEC receive.
SCLK_C
OCZ
CODEC clock.
SFRM_C
OCZ
CODEC frame signal
UDC+
ICOCZ
Serial port zero bidirectional, differential signalling pin (UDC).
UDC
ICOCZ
Serial port zero bidirectional, differential signalling pin (UDC).
TXD_1
OCZ
Serial port one transmit pin (UART).
RXD_1
IC
Serial port one receive pin (UART).
TXD_2
OCZ
Serial port two transmit pin (IrDA).
RXD_2
IC
Serial port two receive pin (IrDA).
TXD_3
OCZ
Serial port three transmit pin (UART).
RXD_3
IC
Serial port three receive pin (UART).
GP 27:0
ICOCZ
General-purpose input output.
SMROM_EN
IC
Synchronous mask ROM (SMROM) enable. This pin is used to determine if the boot ROM (static memory
bank 0) is asynchronous or synchronous. If asynchronous, boot ROM is selected (SMROM_EN = 0) and
its width is determined by the state of the ROM_SEL pin. SMROM is supported only on 32-bit data bus-
ses.
ROM_SEL
IC
ROM select. This pin is used to configure the ROM width. It is either grounded or pulled high. If ROM_SEL
is grounded, the ROM width is 16 bits. If ROM_SEL is pulled up, the ROM width is 32 bits.
PXTAL
IC
Input connection for 3.686-MHz crystal (non-CMOS threshold).
PEXTAL
OCZ
Output connection for 3.686-MHz crystal (non-CMOS level).
TXTAL
IC
Input connection for 32.768-kHz crystal (non-CMOS threshold).
TEXTAL
OCZ
Output connection for 32.768-kHz crystal (non-CMOS level).
PWR_EN
OCZ
Power enable. Active high. PWR_EN enables the external VDD power supply. Deasserting it signals the
power supply that the system is going into sleep mode and that the VDD power supply should be
removed.
BATT_FAULT
IC
Battery fault. Signals the SA-1110 that the main power source is going away (battery is low or has been
removed from the system). The assertion of BATT_FAULT causes the SA-1110 to enter sleep mode. The
SA-1110 will not recognize a wake-up event while this signal is asserted.
VDD_FAULT
IC
VDD fault. Signals the SA-1110 that the main power supply is going out of regulation (shorted card is
inserted). VDD_FAULT will cause the SA-1110 to enter sleep mode. VDD_FAULT is ignored after a wake-
up event untill the power supply timer completes (approximately 10ms).
nRESET
IC
Hard reset. This active low signal is a level-sensitive input used to start the processor from a known
address. A low level will cause the current instruction to terminate abnormally, and the on-chip caches,
MMU, and write buffer to be disabled.
When nRESET is driven high, the processor will restart from address 0. nRESET must remain low until
the power supply is stable and the internal 3.686-MHz oscillator has come up to speed. While nRESET is
low, the processor will perform idle cycles.
Name
Type
Description
