PC-UM10M
SL-5500 HARDWARE DESCRIPTION
– 15 –
(2)-6. PCM AUDIO INTERFACE
(2)-6-1. Outline
• The registers of this module are initialized when the BATTFAULT pin
input level is at LOW.
• This module is not affected by pwren pin input.
• Converts audio data from Ti Audio Format generated by the SSP of
the CPU into Standard Data Format.
(2)-6-2. Block diagram
(2)-7. AUDIO CLOCK
(2)-7-1. Outline
• The registers of this module are initialized when the BATTFAULT pin
input level is at LOW.
• When pwren pin input level is at LOW, the output of mclk and clk64fs
pins becomes LOW regardless of the register settings.
• Capable of monitoring the same signal as those from MCLK /
CLK64FS pins using the status register (04h) bit 0 (MCLK) / bit0
(CLK64FS).
(2)-7-2. Block diagram
(2)-8. GENERAL-PURPOSE 8-bit 2ch DAC CONTROL
SIGNAL
(2)-8-1. Outline
• The registers of this module are initialized when BATTFAULT pin input
level is at LOW.
• The operation of this module does not depend upon the input level of
the pwren pin.
Buffer of each pin:
SCL OUTPUT N-CH Open Drain 5-V withstand voltage, 2mA
SDA INPUT 5-V withstand voltage, 2mA (not a feed-through current
prevention
buffer)
(2)-8-2. Block diagram
(2)-9. TFT-RELATED SIGNAL
(2)-9-1. Outline
• The registers of this module are initialized when the BATTFAULT pin
input lever is at LOW.
• The operation of this module does not depend upon pwren pin input
level.
(2)-9-2. Block diagram
(2)-10. INTERRUPT CONTROLLER
(2)-10-1. Outline
• The registers of this module are initialized when batterfault pin input
level is LOW.
• The operation of this module does not depend upon pwren pin input
level.
(2)-10-2. Block diagram (Here is a circuit image.)
LRCEN
SCEN
LRCINV
LRCEVE
LRCRST
SCINV
TiAudio Format
Standard Data Format
Initialize
sclk
pin
sfrm
pin
CPU bus
lrclk
Reset
lrclk
Leading
and trailing
sclk
Inversion
Register settings
dacsck
output pin
lrclk
output pin
battfault
input pin
lrclk
Inversion
XSEL
XON
XEN
CLKSEL
[2:0]
MCLKEN
CLK64FS
EN
3
Xout24m output pin
Xin24m input pin
Xout22m output pin
Xin22m input pin
CPU bus
Dividing
circuits
Register settings
Initialize
Internal status register
bit10(MCLK)
MCLK
output pin
Internal register
bit*(CLK64FS)
CLK64FS
output pin
battfault
input pin
48KHz System
44
.1KH
z
S
y
ste
m
F/F
F/F
F/F
F/F
3.3~
5.0V
2ch
1ch
CPU
bus
Register settings
Initialize
DAC power supply ON
sda
Input pin
scl
output pin
battfault
input pin
sda
I/O pin
scl
input pin
Power supply
ON/OFF
General-purpose
8-bit DAC
(Mitsubishi
M62332FP)
LCD
COMADJ
Backlight
voltage
light
control
DO
DI
SDA
SDAOEB
SCLOEB
CPS[3:0]
CPSOUT CPSEN
TFTC
RST
F/F
D
O
CK
DCLK_PA20
HS_PA21
PA22
Scoop
(PCMCIA GA)
VCC3
RGB[
5:6:
5]
FNA
B
VS
HS
DCLK
CPU(SA1110)
LCDC
HS
PS
PS
REM
hs pin
dclk pin
CPU
bus
CPS generation circuit
Delay amount
setting
CPS inversion
Register settings
Initialize
cps
output pin
tftreset
output pin
battfault
input pin
TFT panel
controller
TFT panel
Intact
SPIIS
LTIS
GPIOIS
KIS
KIE
GPIOIE
LTIE
SPIIE
INTB
SPI
interrupt
Long-hour
timer
interrupt
GPIO
interrupt
Key
interrupt
CPU bus
Interrupt
status
Interrupt source allowed
Interrupt status
of entire GA
int_b
pin
