Sharp Zaurus SL-5500, Service Manual

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PC-UM10M
SL-5500 HARDWARE DESCRIPTION
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2-6. TIMING CONTROL IC (LZ9GG314)
(1) FEATURES
The LZ9GG314 is a timing control IC for TFT-LCD modules.
Applicable model: Modules using QVGA pixel digital driver
(1) Generates, by inputting the clock signal, horizontal synchronous
signal, and vertical synchronous signal, the following signals which
synchronize with them:
1) Source driver drive signals: CLK, SPL, SPR, LP, PS
2) Gate driver drive signals: CLS, SPS
3) Signal for generating common electrode drive signal: REV
4) Base signal generation signal: REVV0
(2) Capable of inverting the display screen upside down and horizon-
tally.
(2) PIN CONFIGURATION DIAGRAM
(3) SIGNAL DESCRIPTION
Pin
No.
Signal
name
Description I/O
1 DCLK Data clock signal input pin I
2 TESTI Test input pin. Usually set to H I
3 R0 Red data signal input pin I
4 R1 Red data signal input pin I
5 R2 Red data signal input pin I
6 R3 Red data signal input pin I
7 R4 Red data signal input pin I
8 R5 Red data signal input pin (MSB) –
9 GND Grounding power supply pin –
10 VDD Power supply input pin I
11 G0 Green data signal input pin I
12 G1 Green data signal input pin I
13 G2 Green data signal input pin I
14 G3 Green data signal input pin I
15 G4 Green data signal input pin I
16 G5 Green data signal input pin (MSB) I
17 TESTI Test input pin. Usually set to H I
18 B0 Blue data signal input pin (LSB) I
19 B1 Blue data signal input pin I
20 B2 Blue data signal input pin I
21 B3 Blue data signal input pin I
54 37
1 18
55 36
72 19
OR4
OR3
OR2
OR1
OR0
GND
CLS
SPS
VDD
GND
UBL
VRVE
N.C.
N.C.
TV
TESTI
HS
VS
LP
SPL
LBR
SPR
PS
REVV0
REV
RESET
GND
VDD
ENAB
HRVE
B2
B1
DCLK
TESTI
B5
B4
B3
G5
VDD
G0 G1
GND
G2 G3 G4
0G5
TESTI
R0 R1 R2 R3 R4 R5
OB1
TESTI
B0
OR5
GND
OG0 OG1 OG2 OG3 OG4
GND
CLK
L Z 9 G G 3 1
OB2 OB3 OB4 OB5
GND
VDD OB0
22 B4 Blue data signal input pin I
23 B5 Blue data signal input pin (MSB) I
24 TESTI Test input pin. Usually set to H I
25 HRVE Right and left inversion setting pin. Usually set
to H. Set to L for inversion. I
26 ENAB Horizontal display position signal input pin I
27 VDD Power supply input pin –
28 GND Grounding power supply pin –
29 RESET Initialization reset signal input pin. Give the sig-
nal which changes L level to H level and holds it
when power is turned on I
30 REV Common electrode generation signal output pin O
31 REVV0 Base voltage generation signal output pin O
32 PS Source driver control signal output pin O
33 SPR Source driver start signal output pin. (High
impedance other than when it is used for right
and left inversion and ordinary display.) O
34 LBR Right and left inversion display control signal
output pin O
HRVE When set to H: H level output
When set to L: L level output
35 SPL Source driver start signal output pin
(High impedance other than when it is used for
right and left inversion and ordinary display.) O
36 LP Source driver data transfer signal output pin O
37 CLK Source driver clock signal output pin O
38 GND Grounding power supply pin –
39 OB5 Source driver blue data signal output pin (MSB) O
40 OB4 Source driver blue data signal output pin O
41 OB3 Source driver blue data signal output pin O
42 OB2 Source driver blue data signal output pin O
43 OB1 Source driver blue data signal output pin O
44 OB0 Source driver blue data signal output pin (LSB) O
45 VDD Power supply input pin –
46 GND Grounding power supply pin –
47 OG5 Source driver green signal output pin (MSB) O
48 OG4 Source driver green signal output pin O
49 OG3 Source driver green signal output pin O
50 OG2 Source driver green signal output pin O
51 OG1 Source driver green signal output pin O
52 OG0 Source driver green signal output pin (LSB) O
53 GND Grounding power supply pin –
54 OR5 Source driver red data signal output pin (MSB) O
55 OR4 Source driver red data signal output pin O
56 OR3 Source driver red data signal output pin O
57 OR2 Source driver red data signal output pin O
58 OR1 Source driver red data signal output pin O
59 OR0 Source driver red data signal output pin (LSB) O
60 GND Grounding power supply pin –
61 CLS Gate driver clock signal output pin O
62 SPS Gate driver start signal output pin O
63 VDD Power supply input pin –
Pin
No.
Signal
name
Description I/O