PC-UM10M
SL-5500 HARDWARE DESCRIPTION
– 12 –
(6) HARDWARE INTERFACE
2-3. 256Mbit SDRAM (K4S561633C-RL75)
(1) DESCRIPTION
The K4S561633C is 268, 435, 456 bits synchronous high data rate
Dynamic RAM organized as 4 x 4, 196, 304 words by 16 bits, fabricated
with SAMSUNG’s high performance CMOS technology. Synchronous
design allows precise cycle control with the use of system clock and I/O
transactions are possible on every clock cycle. Range of operating fre-
quencies, programmable burst length and programmable latencies
allow the same device to be useful for a variety of high bandwidth, high
performance memory system applications.
(2) PIN CONFIGURATION
(3) PIN FUNCTION
2-4. 64Mbit FLASH MEMORY (LF28F640BX)
(1) DESCRIPTION
The LH28F640BX series page-mode dual-work flash memory has the
following features.
• Dual work function
• Settable partition configuration
• Page buffer program
• Data protection function for each block and full-block lock function at
power-on.
• 8-word OTP (One Time Program) block
• Low power consumption
• Parameter block configuration
TELOP
Relay
ON/OFF
TELON
SCLK
SSYNC
SDIN
SDOUT
TELIP
TELIN
VBO1P
VBO1N
VBI1P
VBI1N
VBI2P
VBI2N
IRQ
-RST
TEST1
TEST2
TSPY
TSPX
TSMY
TSMX
VBO2P
VBO2N
DVDD1 to
DVDD2
DVSS1 to
DVSS2
AIN0
AIN1
AIN2
AIN3
AVDD1 to
AVDD2
AVSS1 to
AVSS2
CVSS1 to
CVSS2
VREF
GPIO[9:0]
TC35143AF
Hand-set
Microphone
Speaker
Digital
power
supply
Digital
grand
Analog
power
supply
Analog
grand
SIB
I/F
Touch
Screen
Power
Supply
Main Battery
Backup Battery
SIB master processor
System
Analog signal
NCU control
Detection
of telephone
line
54Ball (6 x 9) CSP
1
2
3
7
8
9
A
VSS
DQ15
VSSQ
VDDQ
DQ0
VDD
B
DQ14
DQ13
VDDQ
VSSQ
DQ2
DQ1
C
DQ12
DQ11
VSSQ
VDDQ
DQ4
DQ3
D
DQ10
DQ9
VDDQ
VSSQ
DQ6
DQ5
E
DQ8
NC
VSS
VDD
LDQM
DQ7
F
UDQM
CLK
CKE
CAS
RAS
WE
G
A12
A11
A9
BA0
BA1
CS
H
A8
A7
A6
A0
A1
A10
J
VSS
A5
A4
A3
A2
VDD
Pin Name
Pin Function
CLK
System Clock
CS
Chip Select
CKE
Clock Enable
A0~A12
Address
BA0~BA1
Bank Select Address
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
L (U) DQM
Data Input/Output Mask
DQ0~15
Data Input/Output
VDD/VSS
Power Supply/Ground
VDDQ/VSSQ
Data Output Power/Ground
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
G
H
J