Sharp FO-CC500, Service Manual

Page: 68 / 162

FO-CC500A
FO-K01A
5 – 18
Controller Interface
122 DATA0 B-PUP Data bit 0
121 DATA1 B-PUP Data bit 1
120 DATA2 B-PUP Data bit 2
119 DATA3 B-PUP Data bit 3
118 DATA4 B-PUP Data bit 4
117 DATA5 B-PUP Data bit 5
116 DATA6 B-PUP Data bit 6
115 DATA7 B-PUP Data bit 7
15 ADDR0 T Address bit 0
16 ADDR1 T Address bit 1
17 ADDR2 T Address bit 2
18 ADDR3 T Address bit 3
19 ADDR4 T Address bit 4
20 ADDR5 T Address bit 5
21 ADDR6 T Address bit 6
22 ADDR7 T Address bit 7
51 ADDR8 T Address bit 8
52 ADDR9 T Address bit 9
55 ADDR10 T Address bit 10
53 ADDR11 T Address bit 11
46 ADDR12 T Address bit 12
50 ADDR13 T Address bit 13
49 ADDR14 T Address bit 14
47 ADDR15 T Address bit 15
48 WRP (Note 2) T Write; active low
54 RDP T Read; active low
112 ROMCSP O2 ROM chip select; active low
79 RAMCSP O2 RAM chip select; active low
83 HOSTCSP O2 Host chip select; active low
84 HOSTACK IS-PUP Host input acknowledge
82 SYNC (Note 2) O2 Synchronize, CPU fetching OP code
81 NMIP IS-PUP Non-maskable interrupt; active low
85 XCODEP I-PUP Emulator select; active low
80 EMUCLK (Note 2) O2 Phase 2 clock output from MC19
RF Interface
89 REFOSC B4 9.6 MHz clock used by synthesizer
102 RXIN I-A Receiver I negative differential input
101 RXIP I-A Receiver I positive differential input
104 RXQN I-A Receiver Q negative differential input
103 RXQP I-A Receiver Q positive differential input
106 AUXREF B-A AUXDAC reference
100 TXDATA O-A Transmitter data
105 AGC O-A AGC control
110 TRSW O Transmit=1/receive=0 select
108 TXEN O Transmit enable
76 RXEN O Receive enable
75 GPIOC1 O General purpose I/O. Can be configured as LNA select (LNAATN).
111 GPIOC2 O General purpose I/O. Can be configured as PA power level select (TXPWR0).
MERLIN ASIC XROM (R6815): Terminal description
Pin No.
Pin Name Type (Note 1) Description